Hi All, In 8-bit microcontrollers which has upper 128 bytes of internal indirectly addressable RAM, Is stack initilizes from this upper or lower internal RAM address?
Thanks and Regards, Ashutosh Tiwari
"the answer to your question will be totally different"
I don't understand why you say that.
The CPU will always default the stack pointer to 8 on a reset.
Regardless of whether you write code in C or Assembler, there will always be some startup code (Keil supplied or otherwise) that may set the SP to anywhere suitable for the required memory map.
Jack Sprat :-)
In C it is initialized by Startup.a51, In assembly it is (better be) initialized by you.
leaving it at 8 (the reset value) without (Startup.a51/you) initializing it to the correct (app dependent) value WILL lead to disaster.
Erik
"...value WILL lead to disaster."
Actually, for technical correctness, that should read:
"...value MAY lead to disaster."
It really does depend upon what the memory map of DATA/IDATA is as to whether a problem might occur.
Consider ... The map is configured to have a stack starting in register bank one, then there is (arguably) no need to set the stack.
Consider ... The map is configured to have a stack starting in register bank one, then there is (arguably) no need to set the stack. I have no idea what whatever map you are talking about is configured to.
However, leaving the stack pointer at 8 is, of course, possible if your world is upside down and you start allocating variables from the top.
"...if your world is upside down and you start allocating variables from the top."
Very droll!
It would hope that Intel had a valid reason for setting the SP to 8 in their original design.
they also set the SCON to zero, all ports to 1 and the IE to zero. indicating that all reset values are to be considered 'safe' rather than 'working values'
Is there, or have there ever been, any 8051 without any internal RAM besides the SFR region?
The smallest Atmel AVR chips uses the normal registers as a stack. Quite enough to do funny things with a tiny 8-pin chip.
"...considered 'safe' rather than 'working values'"
Either way, they are both predictable and usable - Heck, I wouldn't be too happy if the processor reset state were to allow interrupts to occur after the reset and before I had a chance to configure the interrupt sources as required.