I'm having problems with 8051 based ISRs. The problem occures when:
1- Interrupt A is being serviced. 2- Interrupt B occures and is serviced (in the middle of ISR A execution. 3- Sometimes ISR A fails to complete.
I'm using the C ISRs used in C51 without any register set defined ("using xx"). My understanding is that the ISRs should get entered and serviced mutually exclusive from one another without corrupting one another's stack. Is this not the case?
The term "error prone" makes it sound so incredibly dangerous. It's not. It just requires a little careful consideration. Just like most (non-trivial) programming tasks.
With regards to your trick ... Yes, I agree it is another useful technique. I have done the very same thing on a number of occasions (on a number of different CPU cores).
The term "error prone" makes it sound so incredibly dangerous. It's not. it is for some
"it is for some"
As is walking across the road, but that doesn't mean people should never do it!