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Keil 8051 interrupt ISR

I'm having problems with 8051 based ISRs. The problem occures when:

1- Interrupt A is being serviced.
2- Interrupt B occures and is serviced (in the middle of ISR A execution.
3- Sometimes ISR A fails to complete.

I'm using the C ISRs used in C51 without any register set defined ("using xx"). My understanding is that the ISRs should get entered and serviced mutually exclusive from one another without corrupting one another's stack. Is this not the case?

Parents
  • you say: "(carefully) crafting" [I would drop the paranthesis]
    I say "error prone"

    same thing just from different directions

    There is, another trick that is valuable (and I have used) in some cases:
    I use T0 as the example of the interrupt you just happen not to use, any unused interrupt will do.
    Set all interrupts except T0 to high priority, take what overloads the interrupt out and put it in the T0 ISR. In the now no more overloading ISR set TF0.

    Erik

Reply
  • you say: "(carefully) crafting" [I would drop the paranthesis]
    I say "error prone"

    same thing just from different directions

    There is, another trick that is valuable (and I have used) in some cases:
    I use T0 as the example of the interrupt you just happen not to use, any unused interrupt will do.
    Set all interrupts except T0 to high priority, take what overloads the interrupt out and put it in the T0 ISR. In the now no more overloading ISR set TF0.

    Erik

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