Hello All,
If anybody has ever looked through the spec document, chapter 8 talks about parallel io. There is a subsection that talks about how to go ahead and add additional TTL I/O using the CE . For the chip, CE is not available (according to the api) so the CE method is what I am trying to implement.
I have built the circuit minus the decoder since I will not be needing the address bus. There is an example program and layout they list to test the additional circuit and mine is not working. I have been able to see with an oscilloscope the CE signal working as well as the write signal. PSEN does nothing when I run the simple test program. I know PSEN is connected properly since it does things when slush is booting up. Has anybody tried to implement the circuit that I have mentioned? I appreciated any response.
DJNOCLUE
If anybody has ever looked through the spec document,
There are several hundred 8051 derivates, each with its own datasheet. How is anybody supposed to know which of them you're talking about?
Has anybody tried to implement the circuit that I have mentioned?
Somebody probably has, but since they don't know which circuit you're talking about, nobody knows if they're that somebody.
they list and who are 'they'?
Erik