Hello, I have been reading the details concerning interrupt handling in the ARM core. I see how nested/not nested interrupts work, and that it is important to clear the interrupt in the handler to prevent an infinite loop. I see the assembly instruction for that, too. But why don't I see something similar when I compile the code for a C166? What did I miss?
Thanks in advane, Cactus Blip
I don't know the ARM but on the C166 most interrupts are cleared automatically by the hardware when you vector to the ISR. Interrupts are still active and if any interrupt becomes active that has a higher level then the current one it will vector to it. There are exceptions such as the NMI which will result in an endless loop unless the software clears the flag.
I don't know why you are reading an ARM manual and wondering why the C166 does act the same way. In my opinion it is like comparing apples to oranges.
What did I miss?
How one particular interrupt controller works is described in its documentation (different ARM7 chips may even have different interrupt controllers). Using one interrupt controllers documentation to make guesses about how a different controller works is fairly pointless.
Hello, That is true - I guess that's why I am called Cactus Blip :) :) :) In other words - curiosity.
Chris, Thanks for your reply. I am only interested in a brief description of the cause out of curiosity. see previous statement: "Hello, That is true - I guess that's why I am called Cactus Blip :) :) :) In other words - curiosity."
Cactus