C164ci Simulation - Show CAPCOM pin toggling in Logig Analyzer

Assuming you have

#define D_PWM1 CC60
#define D_PWM2 CC61

I would also change latching of the period and starting of T12.

  /* PWM0 and PWM1 signal frequency configuration */
  D_PWM1 = 1;
  D_PWM2 = 1;

  /* Configuration of the PWM outputs */
  CC6MSEL = 0x0022;

  /* 10230 = 100% full scale */
  T12P = 10230;
  T12OF = 0;

  /* 5V -> 10bits */
  CTCON = 0x001C;

Then you need to configure two pins in the "Setup Logic Analyzer" screen.

For one:
Current Logic Analyzer Signals: PORTL1 -> Bit -> And Mask 2 -> Shift Right 1

For the other
For one:
Current Logic Analyzer Signals: PORTL1 -> Bit -> And Mask 8 -> Shift Right 3

Hope this helps

Hi,

thank you Chris for your answer. I missed to say that I have configured:

// PWM Management Pulse Width Modulation
sbit D_PWM1 = D_PORT1_L ^ 1; /* dport1L */
sbit D_PWM2 = D_PORT1_L ^ 3; /* dport1L */

to setup up the pins (I want to use 2 PWMs) as output.
I use CC60 and CC61 for setting up the PWM width.

But the point is, is there anything wrong configured ?
I do not get any toggling visible within the Logic Analyzer. I have tried nearly every possible configuration. Of cause I am using P1.3 within the Logic Analyzer setup, I guess this is not the problem, I could make other signals visible no problem. But I do not see any toggling on P1.1 and P1.3 which must be visible if the CAPCM is running.

Is this a simulation problem of the C164ci target or is the CAPCOM not configured as running ??

Thank you in advance for any hints,
Sammy

Here is your example that demonstrates PWM on P1L.1 and P1L.3 using the simulator.

#include <reg164ci.h>

void main(void) {

  /* Configuration of the PWM outputs */
  CC6MSEL = 0x0022;

  /* Period = 10230 */
  T12P = 10230;
  T12OF = 0;

  /* PWM0 and PWM1 50% DC */
  CC60 = 10230 >> 1;
  CC61 = 10230 >> 1;

  CTCON = 0x001C;

  for(;;);
}

-Chris

Hi Chris,

thank you very very much for your help :-))
I can now simulate the output of the CAPCOM6 within the Logic Analyzer, using exactly your code. :-))
For viewing pin toggling within the Logic Analyzer I need to setup the VTREGs of the ports PORT1L.1 and PORT1L.3.

Great it works,
Sammy