Aduc842: Doubts about timer2 and timer3.

I'm using the Aduc842 with a 32.768KHz crystal. I want to use the Analog to Digital Converter and I want to get 8000 samples per second. I'm using timer2 for the interrupt of ADC.
Let me assume it is a 6 clocker and then at 32kHz you get ~5000 instruction cycles (~2000 instructions) executed per second. That makes it darn difficult to get 8000 samples in that time. even if it was a one-clocker (I have heard of no oneclockesr but the SILabs) you would not be able to process a sample in 4 instruction cycles (~2 instructions)

also
I also want to send via UART some data with 115200 baudrate that I generate with timer3
put that into the Keil baudrate calculator http://www.keil.com/c51/baudrate.asp together with your clock speed and see.

As stated above, I assume about a chip I do not use, If it has a PLL or some such thing I am totally off the rocker.

I guess you need to clarify some things and a link to the datasheet would be nice.

Erik

That chip has an on-chip PLL indeed.

The 5.722us is the Timer2 cycle time.

What the final PLL-output frequency?

how can you tell
The 5.722us is the Timer2 cycle time.
when you have to ask
What the final PLL-output frequency?

Erik

Thanks for your answers.

Here you have the datasheet of the microcontroller: www.analog.com/.../ADUC841_842_843.pdf

As the datasheet says:

The ADuC842 and ADuC843 are intended for use with a
32.768 kHz watch crystal. A PLL locks onto a multiple (512) of
this to provide a stable 16.78 MHz clock for the system.

At 5 V the core clock can be set to a maximum of 16.78 MHz,
while at 3 V the maximum core clock setting is 8.38 MHz. The CD bits should not be set to 0 on a 3 V part.

So, in my case (maximum 8,38MHz), PLL control register should be PLLCON=0x001.

And reading the Timer 3 Generated Baud Rates' formulas I find that for 115200 baudrate T3CON=0x082 (DIV=2) and T3FD=0x009.

To control the analog to digital converter I use timer2. I want a 125us sample period. I know timer2 reload period depends on the PLL frequency, but how can I calculate it?

if AD has not 'deviated' T2 will run at SYSCLK/2 so the 'step time for T2 will be 1/SYSCLK ~ 238ns. so you must set RCAP to 65536 - x where x = 125000/238.

please verify

Erik