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MCBSTR9 ethernet maximum throughput at 96MHz

Firin Bol

I am using MCBSTR9 evaluation boards for testing the ethernet throughput (sending 1316 bytes length UDP packets).

I have implemented my code using the Keil HTTP demo with RTX_Kernel and running the board at 96MHz.

The maximum speed I got is (aprox) 40Mbit/s but I have two questions:

1. Is it possible to set FMICLK = RCLK = 96Mhz (now is RCLK/2) ?? (PLL config (2,192,25), Or there is any kind of speed limitation??

2. Is there any other TCP/IP stack optimized for this board to get a higher throughput??

thanks,

Firin

  • 0

    There are other settings you can optimize:

    1. enable PFQBC unit (STR91x.s)

       System Configuration - SCU_SCR0 - EN_PFQBC


    2. disable DTCM wait state (STR91x.s)

       System Configuration - SCU_SCR0 - WSR_DTCM


    3. disable AHB wait state (STR91x.s)

       System Configuration - SCU0_SCR0 - WSR_AHB


    4. set FMI wait states to 1 Wait State

       Flash memory Interface - WSTATES

    With those changes you will have much better benchmark results.

    You can set FMICLK = RCLK = 96Mhz for new STR912FA devices not for STR912F.

    Franc

  • 0 in reply to Franc Urbanc

    Thank you very much Franc.

    I have changed all these settings and the performance is much better, specially enabling the pre-fetch QBC unit.

    Regards,

    Firin