Howdy -- I'm starting with Cortex M processors, but I have lots of experience with 8bit MCUs.
I have been working on learning the STMicro PAL headers.
One thing, coming from an 8051, is that you can individually set/read pins. I didn't think this was significant, until I kind of started looking at the HAL headers and realized there doesn't seem to be similar functionality.
In 8051 with the Keil compiler, you do something like:
sbit LedOutput P2^5;
Is this not the Cortex M way to accomplish bit level reads like that?
Like I was taken aback that there is an BSRR and BRR registers. No such concepts on 8051s.
THERE IS AN EPIC THREAD ON THIS FROM 9 YEARS AGO: http://www.keil.com/forum/15029/direct-referrence-to-gpio-pins/
Near the end of this masterpiece post, there is some discussion of bit banding and reading individual bits in the works for M3's.
Did this ever come to fruition for M0's?
In the STHeaders, define all the individual registers, with shifts and masks. So it seems like bit level access is not the way this works in 2018.
If you want to read an individual register, is shifts and masks the most efficient way to get the job done on a Cortex M0?
"STMicro PAL (sic?) headers"
Do you mean "HAL" ?
"the Cortex M way"
It has nothing to do with Cortex-M.
Cortex is just the CPU core - nothing to do with peripherals.
The GPIOs - and other peripherals - are entirely proprietary to the chip maker. Nothing to do with ARM or Cortex.
No. I am talking about the CMSIS-HAL for my particular MCU. Have YOU ever heard of it?
Also, if bit-banding is not applicable to ARM cores. Please tell me why the ARM Information Center details so much about it, in the Cortex-M System Design Kit Technical Reference Manual.
infocenter.arm.com/.../index.jsp
Right because it has nothing to do with Cortex M's...
You are such an @sshat sometimes. I don't get it.
And before you start some pedantic battle about the CORE vs. the VENDOR PERIPHERALS.
"Bit-banding is a term that ARM uses to describe a feature that is available on the Cortex M3 and M4 CPU cores. "
Save yourself the time. You are being a prig. I feel sad for you, because you must enjoy writing posts for the sole purpose off being a prig. I don't get it.
--- To anyone else:
Is it safe to say that bit-banding is optional on Cortex M0's right now?
Typically included on Cortex M3/M4s.
www.nxp.com/.../AN4838.pdf
Here is a good write-up from SI Labs circa 2013:
"Interestingly, despite bit-banding offering the best code density for register-level bit manipulation, it is not part of the Cortex-M0+ core which ARM has targeted for the smallest, most cost-sensitive microcontrollers. For these kinds of devices, ARM recommends that designers implement dedicated set/clear registers, which have the benefit of drawing current only when clocked versus the bit-band address decoder, which is probably clocked for all memory accesses."
www.silabs.com/.../bit-banding_vs_trad-xp1l
(Emphasis for you Andy. Stop being a prig). ---
Has this changed for M0's?
I can't comment on what cores offer bit banding, but I would say this:
Your initial example; i.e.,
Is typically used to so that you can set/clear/test an individual port pin.
Many processors with ARM cores (or at least, many I've read datasheets of) have registers specific to individual operations such as set/clear/test and can be used to carry out the desired operation on one or a combination of bits.
Some processors go further and allow you to do other things at the bit level, such as toggle the bit.
Using these registers, it is easy to create macros for individual bit control.
When I first looked at ARM I looked into bit banding for creating an equivalent of the C51 Bit for variables, but in truth I've not yet found a need in my applications to use it.
The registers for manipulating individual port pins has clear uses and it is something I look for when choosing a processor for a task.
(Apologies if this response appeared prigish ;) )
The CM0 does not support bit banding.
The CM3/CM4 usually supports two regions, on the STM32's usually the SRAM and Peripheral
Bit banding is achieved through a secondary memory space where each word represents a bit in the primary, and the core does a read-modify-write operation to change bits. Books like those from Joseph Yiu might better explain the concept.
For GPIO registers there is the BSRR which sets/clears bits as it writes through to the ODR register.
The CM0 has a reduced number of features, but is basically a load/store RISC core, and as such doesn't do complex RMW against memory, you decompose those into multiple instructions that still work faster than the complex forms offered by the 8051. There isn't the concept of SFR or Zero Page memory. Memory is treated in a uniform and consistent manner, and peripheral registers live within the same larger memory space as the FLASH and RAM.
Guys thanks. I think I am getting a grip on it.
So after my outburst, let me just thank you guys for such helpful advice. It really is a huge help to get a nudge in the right direction.
@Mr. Burman, I totally am in your shoes coming from C51 and looking at the GPIO registers. I looked at the HAL functions (getters/setters), and you could tell something was different about the architecture. I don't have an assembly background, having started at this in 2016, but I get the gist (less assembly instructions = better design).
I want to make sure I'm not using a bunch of extra overhead for what seems like such a menial atomic operation on an 8051... I actually didn't even consider/know about the race condition possibility using the ODR register! Good thing to look at this when learning GPIOs on ARM.
I'm on my 8051 software-efficiency kick this month, so might as well get down the optimal way to read an input and toggle an output when getting on to the ARM Cortex M!
[Side note: I get the feeling I am going to use the CMSIS-CORE functions & register definitions, but not use the vendor HAL unless it is required for the middleware. I have to come up with a good project idea for using the middleware for something interesting].
@Pier -- I read somewhere else (circa early 2010, that the BSRR register (and the related ARM IP around it) was licensed by ST specifically. Is it kind of all over the place depending on the ARM vendor? I'm seeing the importance of checking the datasheet on this element... you kind of take it for granted in 8bit world.
>>I want to make sure I'm not using a bunch of extra overhead for what seems like such a menial atomic operation on an 8051
RISC just makes you move things through visible registers rather than letting microcode hide it in invisible ones. The operation that takes dozens of cycles on the 8051 takes 3 cycles to clock along the pipeline in the Cortex, plus some more to complete depending on the bus speeds involved.
Things you can contain in registers take a single cycle, and other things that take multiple instructions and tens of dozens of cycles on an 8051 are done in far fewer or one. Say 32-bit addition, or multiplication, things like division are massively more efficient. The CM0 removes the hardware divider, the software version will significantly outpace the equivalent 8051 implementation.
The "BSRR" operation is just combinational logic around a flip-flop, people have been using for many decades
en.wikipedia.org/.../Flip-flop_(electronics)