Reading from cortex debug + ETM

Thanks for your response. The J-trace has j-tag and cortex debug +ETM support, I am interested in the latter. The stm board has inputs for cortex debug, cortex debug + ETM, and JTAG. The J-trace's plug fits very snugly into the cortex debug +ETM port but with the pins being so close and the fit being so snug, it doesn't seem practical to run wires parallel to that port.

From your response, I take it that the GPIO IDR solution won't be sufficient for any real time application.

So i guess the next best thing is an intermediate board where there would be more room to work with, although that presents its own challenge of needing the proper connector to go from the intermediate board to the stm board. The reason I need to access these pins is for a PhD student I'm working with this summer. She wants to be able to access the pin information from two methods simultaneously.

Thanks again

Thanks for your response. The J-trace has j-tag and cortex debug +ETM support, I am interested in the latter. The stm board has inputs for cortex debug, cortex debug + ETM, and JTAG. The J-trace's plug fits very snugly into the cortex debug +ETM port but with the pins being so close and the fit being so snug, it doesn't seem practical to run wires parallel to that port.

From your response, I take it that the GPIO IDR solution won't be sufficient for any real time application.

So i guess the next best thing is an intermediate board where there would be more room to work with, although that presents its own challenge of needing the proper connector to go from the intermediate board to the stm board. The reason I need to access these pins is for a PhD student I'm working with this summer. She wants to be able to access the pin information from two methods simultaneously.

Thanks again

Not tinkered with this in recent years, but the trace data is a fire-hose data source, so you need some means/method to capture it, and then to process it.

This isn't an olden days ICE type trace, but rather a reconstructive process where you're holding copies of the on board memories, and replicating transactions into a state model of the processor core.

I'd probably go with the pass-thru interposer method, and buffer into an FPGA or FIFO memory.

Perhaps find a different F4 board which you can get to the SWDIO, SWCLK and TRACE pins more directly?

Or a board exposing the pins?
www.segger.com/.../cortex-m-trace-reference-board-v1_2-3d-1000x.png

This: www.segger.com/.../ ?

I have found this type of adaptor useful for adapting that kind of small connector up to 0.1" pitch:

uk.farnell.com/.../2476039

You could use a 2nd one to adapt back down again for a pass-through board ...

Relly helpful for me. I will buy this one www.segger.com/.../ for my connector to 0.1 pitc.