Hi,
Using the STM32F401RE uC I wonder where the clock signal CK_INT is originating from as is shown in a Timer1 figure. I searched al the reference manual but did not find it. As my SysClk is 30MHz, checked with the MCO2 output by oscilloscoop and all AHB and APB prescalers are set to zero, Timer1 is clocked with 15MHz as I can check by toggling a GPIO on the update interrupt (TIM1_UP_TIM10_IRQHandler) with reload value of 10.000. It should be 30MHz. Do I mis some divider?
Thanks
Henk
CLK_INT would be from the APB divider chain to which the TIM is attached, per the Clock Tree Diagram.
In all but the DIV1 case the clock feed to the timer is 2X that of the APB. The ratios of the clocks are set up in the RCC.
If the part clocks at 84 MHz, and APB2 is 84 MHz (DIV1), and APB1 is 42 MHz (DIV2), then TIM2 on APB1 would clock at 84 MHz internally.
Toggling halves frequency.
How would 10 or 10000 get you to 30 MHz? If the CPU/APB1/APB2 all clock at 30 MHz (ie DIV1) then the TIM would clock at 30 MHz, toggling a GPIO with a Period of 10000-1 (N ticks programmed as N-1) the interrupt would occur at 3 KHz, a toggled pin would scope at 1.5 KHz
thanks for your comment.
I measured the time between 2 toggles being 666ns so the Timer1 input klok would be 666us divided by preload value 10.000 making it 66,6ns or 15MHz. I found the origin of the problem. The Timer1 prescaler was set to 1 by accident. I always make this mistake. Setting the prescaler value to 1 makes it divide by 2. (the prescaler value is NOT the divider value...) After setting it to 0 the toggle time is now 333us which confirms that SysClk indeed is 30MHz.
Thanks anyway!
(love timers if they do understand me...)
The Prescaler and Period values are both end values for counters, and act as dividers
ie
Prescaler = P - 1; // Always 16-bit integer Period = Q - 1; // 16 or 32-bit depending on counter
UpdateFreq = INT_CLK / (P * Q)
I don't expect the processor to interrupt at MHz rates
The timer channels can be set in toggle mode, this doesn't require interrupts.