This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

stm32f429 external memory

are there facilities for implementing external memory or do I have to make a function that write row, write colunmn, read/write data?

  • Within the addressable space of the processor, reads and writes like normal memory

    Configured via FMC or FSMC controller, describing width, banks, rows and columns are required.

    Writing NAND or NOR FLASH would require gyrations per respective part data sheets.

  • I'm confoosed, both tose talk about 'file system' I want to access it as RAM

  • I'm confoosed, both tose talk about 'file system' I want to access it as RAM

    Not sure what tose (those) you are talking about. I am not seeing any reference to "file system" in Westonsupermare's post. He was just mentioning that accessing flash can mean more than just doing a memory read/write. Since you are not accessing NOR or NAND flash, you will not need to go through any "gyrations"

    When you configure the FMC, you are telling the processor how to specifically manipulate the the Address Lines / Data Lines / Read/Write etc. lines connected to the external Memory when a memory READ/WRITE is made to a specific address range. There are multiple address ranges (referred to as Banks) so you can connect more than one type of external memory with different timing associated with it. You configure then in the FMC as Bank1,Bank2...

    Once it is configured your program will reference it like any other RAM/memory device (LDR, STR, x = 5; what ever).

    Look in the SFM32F4 Reference Manual under the Flexible Memory Controller Section (FMC)

    This section discusses configuring the FMC for accessing Static RAM, SDRAM, NOR Flash and NAND Flash.

    For a good example on setting up and accessing SDRAM, look at the examples related to the STM32F429 Discovery board.

  • I'm not sure what you're referring too, the FMC/FSMC is the external memory bus controller, and provides signalling required by the memory devices to be accessible via LDR/STR instructions in the same fashion as internal memory, just slower

  • Maybe the op should ask his teacher for help ;)