Dear everybody,
Currently I am developing a custom chip based on Cortex M0. The chip has an external SRAM that functions as storage for applications and data. I did a test to make sure every bits in the SRAM is able to switch from 0 to 1 and back. I refer to this link for the code barrgroup.com/.../Memory-Test-Suite-C
I load the program to address 0x0 of my SRAM and do the test for address 0x1000 - 0x10000 (64 kB SRAM size, leaving the first 4 kB untested). The problem is that I can't always single step or breakpoints through the code. Sometimes it skipped a breakpoint and most of the time, landed in Hardfault_Handler.
However, when I load the program to RAM (0x20000000), and testing the SRAM from there, the single step and the breakpoints work just fine. Can anybody give a clue about what might happen here? Thanks!
http://www.keil.com/forum/63013/
Perhaps when designing a custom CM0 SoC it would be helpful to understand the processor and subsystems, and how to debug the hw/sw?
If the system is Hard Faulting, understand what the processor is complaining about. Is it a simple alignment fault, or do you have some more serious issue on the memory buses, and your FLASH/ROM subsystem.
Understand what RAM your code is using, the size of stack allocated, and required by your call tree. Look at the stack pointer and other registers when it faults and whether those are outside expectations.
Have the design reviewed by someone with more experience in development, integration and bring-up tasks.