About PCLK

I take it you haven't actually downloaded the PLL spreadsheet from NXP:s site?
And you didn't try my formula either.

PLL0 = 2 * M * FOSC / N = 2 * 10 * 12 / 2 = 120MHz.
But the datasheet §5.1 says the PLL0 requires a frequency 275 - 550 MHz. 120MHz is much too low.

Change M = 12
Change N = 1
Then you get PLL0 = 2*12*12/2 = 288MHz.

With CPUDIV = 4, you then get CCLK = PLL0/4 = 288/4 = 72MHz

With PCLK_DIV = 4, you then get PCLK = CCLK/4 = 72/4 = 18MHz.

Then compute a suitable baudrate divisor to get your required baudrate.

Or select a different set of M, N, CPUDIV and run the CCLK at a different speed - if I remember correctly, some LPC17xx manages 100MHz and some manages up to 120MHz.

If you need really high UART baudrates, you might consider to use a lower PCLK_DIV to not get too large baudrate error from rounding error when computing the baudrate divisor - but that also depends on how high CCLK you configure.

I take it you haven't actually downloaded the PLL spreadsheet from NXP:s site?
And you didn't try my formula either.

PLL0 = 2 * M * FOSC / N = 2 * 10 * 12 / 2 = 120MHz.
But the datasheet §5.1 says the PLL0 requires a frequency 275 - 550 MHz. 120MHz is much too low.

Change M = 12
Change N = 1
Then you get PLL0 = 2*12*12/2 = 288MHz.

With CPUDIV = 4, you then get CCLK = PLL0/4 = 288/4 = 72MHz

With PCLK_DIV = 4, you then get PCLK = CCLK/4 = 72/4 = 18MHz.

Then compute a suitable baudrate divisor to get your required baudrate.

Or select a different set of M, N, CPUDIV and run the CCLK at a different speed - if I remember correctly, some LPC17xx manages 100MHz and some manages up to 120MHz.

If you need really high UART baudrates, you might consider to use a lower PCLK_DIV to not get too large baudrate error from rounding error when computing the baudrate divisor - but that also depends on how high CCLK you configure.

Hi,

you are right. I had the mistake. I followed your notes with M=12,N=1 and found DLL=117 or 0x75.
But I don't receive any character in PC unless I give a value between 1 and 40 for DLL so I receive sth like ????? .
It is confusing!

I think I have not set a proper value in FDR register. Do you have any idea how to set it? I dont understand what is the devideVAL[3:0] and mulVal[7:4]??

By try and error (I mean by using a for() loop) I found that the best values for DLL is 0x5 and for FDR is oxf5.
by these values USART0 works well for Baudrate 9600. But my problem is not solved since I dont know how to config for other values of Baudrate!!! I need your kind help.

Try and error!? why? reading of the user manual is not more difficult than try and error. if you realize the structure of the PLL and clock section, you can set the desired baud rate with 0% error. in edition there is a configuration wizard in start up file that you can manage the system clock if you add it to your project.