I think I have found a bug for ARMCC.
in my case, the correct result which would be:
VCMPE.F32 s0,s1 VMRS APSR_nzcv,FPSCR ITTT LS
But actually, that was:
VCMPE.F32 s0,s1 VMRS APSR_nzcv,FPSCR ITT LS
that was wrong for execute result also, and when i edited the bin file which is compiled and assemblied(change "ITT LS"(0xbf9c) to "ITTT LS"(0xbf9e)), everything looks correctly.
cortex-m4lf (you may see VMPE.F32 and VMRS)
ARMCC 5.6.0.13 in KeilMDK 5.18.0.0
source code likes (but not the same, and i am not sure this will be reproduct that)
#define ARRAY_LENGTH 10 float t0[ARRAY_LENGTH], t1; unsigned char i, arr[ARRAY_LENGTH], count; // do something, assign count, t0, t1, arr; for (i = 0; i < count; i++) { if (arr[i] != 0) // complier has changed these two statement. { if (t0[i] < t1) // complier has changed these two statement. and i donot know how complier make sure t1 is not NaN { continue; } } // do something; }
VCMPE.F32 s0, s1 VMRS APSR_nzcv,FPSCR ITT LS // here should be ITTT LS LDRBLS lr, [r12, #0] CMPLS lr #0 BNE ####### // so this BNE got the wrong flag Z
Compiled by CLR with param "--c99 -c --cpu Cortex-M4.fp -g -O3 -Otime --apcs=interwork --split_sections" (no completely, but I think others are not the key)
Thanks for your prompt reply! i will provide as more info as i can, but except complete source code. even now i cannot confirm is that a bug or just i got the wrong way to use. any way, thank you all again.
there is a mistake, not CLR, just command line.
even now i cannot confirm is that a bug or just i got the wrong way to use.
No point in anyone wasting time looking at it then.
First lesson in hunting a bug: Try to reproduce it.