Keil V5 -- linker adds 20KB of padding to the final image

Hi,
I am using an EFM32ZG108 processor(Cortex M0+) and in my project I need to have In System Programming (write/erase flash whilst the MCU still works). For this I had to move some functions in RAM. I have done that by using
#pragma arm section code="ram_code"
before the functions I want to run in RAM. I have also created my own scatter file to place the ram_code section.

When I use the scatter file the linker adds ~20KB of padding, please see below message.

.\Objects\myProject.axf: Error: L6220E: Load region LR_IROM1 size (33240 bytes) exceeds limit (32768 bytes). Region contains 22324 bytes of padding and 48 bytes of veneers (total 22372 bytes of linker generated content).

This contributes to my RO code and makes my image bigger than 32K -the max flash size of this part.

Here is my scatter file:

LR_IROM1 0x00000000 0x00008000  {    ; load region size_region
  ER_IROM1 0x00000000 0x00008000  {  ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x20000000 0x00001000  {  ; RW data
   .ANY (+RW +ZI)
   *(ram_code)
  }
}

I have noticed that when no dedicated scatter file is used KEIL creates its own in the “project_directory\objects”
When I use the auto generated scatter file (in the Target Options-->Linker-->Scatter File box) I get the exact same behaviour as with mine. It looks like just by using a scatter file in Target Option-->Linker-->Scatter File box the liker generates padding….
I had a look at :
infocenter.arm.com/.../index.jsp
and tried to fix the issue by using --any_contingency with no success.
Can anyone explain to me how to stop the linker from generating the padding?

Thank you,
Vali