i write source for st32f407,that port PE.2 is toggle with delay 1 second for code we use cmsis library. why when in logic analyzer we add signal port PE.2 is has error unknown signal.....!!1 can any help me thanks for reply
So you have problems.
And then you directly visited Google and tried "keil simulation st32f407"
And you very quickly found this thread: www.keil.com/.../
and this Keil link: http://www.keil.com/dd/chip/6103.htm
and your conclusion was to create a new thread to ask why it doesn't work to simulate the chip...
thanks so i should i use stdeugger.