Hello,
I ported a development from F4 processor to L4, and got an error from the compiler, complaining about FLASH_OPTR_nRST_SHDW not defined.
Indeed, it seems its definition lacks in stm32l486.h under STM32L4xx_DFP/1.0.0/Device/Include. This, I was able to deal with.
But when I run a debug in simulation, I finally run into troubles due to bad memory map definitions. Do we still have to define all memory ranges in Debug->Memory map..., or is there somewhere a file which describes the overall processor memory map ?
Or we can also ask: when will there be an update of the DFP for L4 processors ?
Any help is appreciated.
BR,
J.Bray