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understanding the SBUF register

The 8051 has only single SBUF register.
But the datasheet say it can support full duplex. for full duplex communication we must have different buffers(?) for transmitting and receiving.
how a single byte SBUF register work as two registers ?

from the site www.edsim51.com/.../serial.html Unlike any other register in the 8051, SBUF is in fact two distinct registers - the write-only register and the read-only register. Transmitted data is sent out from the write-only register while received data is stored in the read-only register. There are two separate data lines, one for transmission (TXD) and one for reception (RXD). Therefore, the serial port can be transmitting data down the TXD line while it is at the same time receiving data on the RXD line.

how the single buffer register act as two?

Parents
  • Having a read-only + a write-only register on top of each other is quite common. Why create separate data-write and data-read registers when a single "data" register works so well? And what action should the processor then take if someone reads from the write-only register or writes to the read-only register? Adding lots of extra transistors just to cover the corner cases of giving users separate read and write registers?

    Another issue here is that there are often not even a 8-bit + 8-bit buffer "hidden" behind that data registers. On send, it's common to be at least two 8-bit registers. One for the data that gets latched and shifted out and then one other where the program stores the next byte to shift out.

    And on read it's the same thing. One buffer that shifts in new data and one buffer where the program can pick up the last received byte.

    Step up to an improved processor, and send and receive might suddenly get 16-byte FIFO - one in each direction. And accessed through the same 8-bit read + 8-bit write registers overlapping the same address. SBUF isn't a memory cell. It's the interface to a pipe. And the pipe might contain lots if incomming and outgoing data. And what has been dropped off for transmission can't be peeked at again - unless you are at the other side of the pipe where the data will normally arrive some time later.

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  • Having a read-only + a write-only register on top of each other is quite common. Why create separate data-write and data-read registers when a single "data" register works so well? And what action should the processor then take if someone reads from the write-only register or writes to the read-only register? Adding lots of extra transistors just to cover the corner cases of giving users separate read and write registers?

    Another issue here is that there are often not even a 8-bit + 8-bit buffer "hidden" behind that data registers. On send, it's common to be at least two 8-bit registers. One for the data that gets latched and shifted out and then one other where the program stores the next byte to shift out.

    And on read it's the same thing. One buffer that shifts in new data and one buffer where the program can pick up the last received byte.

    Step up to an improved processor, and send and receive might suddenly get 16-byte FIFO - one in each direction. And accessed through the same 8-bit read + 8-bit write registers overlapping the same address. SBUF isn't a memory cell. It's the interface to a pipe. And the pipe might contain lots if incomming and outgoing data. And what has been dropped off for transmission can't be peeked at again - unless you are at the other side of the pipe where the data will normally arrive some time later.

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