Why do we use R0 and R1 in indirect addressing mode of 8051? This question has been answered in one of the threads but i want to know how come 8051 can only select one bit for R0 or R1 and R2 to R7 is not possible. sorry if i sound a little stupid. i am a newbee in 8051
The compiler uses only R0 & R1 because hardware is designed such that only R0 & R1 can be used.
Its our design and we dont like numbers 2-7, hence we designed only for R0 & R1. Do you have any problem with that?
Sorry buddy, but the obtaining of benefits with what was posted above is a bad idea. maybe I didn't say that I have with the language problem (very conceal myself whenever possible to see they were at the elementary sense), but (here I cuss) this too.
I and others here also started (I'm still here I don't really understand) what you must do with R0 and R1. but I fit into the core framework of local processing rules, and you, it seems they march it. I warn you - if you'll use C51 (or my friends), you are certainly reward (free translation).
LOL i have no problems. I have recently started studying 8051 and I am geek in this domain. I have seen examples where data has been loaded into bank registers (R0, R1, R2.... and so on). all these registers are 8 bit registers and are located one above the other in memory. i wanted to know if we can use other registers (R2, R3,...and so on) for data storage then what is the reason behind not using R2-R7 for register indirect addressing? if its because of the internal architecture of 8051 then i would like to know what's so different with registers R2-R7 that they can not be used for register indirect addressing mode. Thanks in advance
Look at the instruction encoding for the instructions that specify indirect addressing.
You'll see that only one bit is available for specifying the register to be used.
It is difficult to get a selection of more than two registers when only one bit is available for that specification.
The 8051 has, as far as I'm aware, never been described as being orthogonal.
I guess you didn't pick up the hint from my original post where I asked "Are you debating why Intel designed the processor instruction set as they did, trying to cram in so [sic!] much information as possible in a byte".
They used about 50000 transistors for the complete processor including timers etc. And the instruction set really has to look different when you try to figure out what to store in one byte (8 lonely bits) compared to a processor who reads 32-bits as minimum size from the memory.