read write on code memory in 8051 using C

Is't only the additional feature I am providing.

It was not in my requirements.

Is it possible now?

Is't only the additional feature I am providing.

It was not in my requirements.

Is it possible now?

Yes it is possible - it's just a question of your "frequently" and how much you care. I _think_ the endurance is 10000 writes - and a sector erase size of 128 bytes. One question is how quick a write or erase is - it can sometimes be a show-stopper. You have to locate the relevant datasheets and figure out exactly what is documented about your chip.

So - how many 128 byte sectors can you dedicate to your counting? And how clever can you be using them? That will control how fast you reach 10k write/erase cycles for each 128 byte sector. Note that the power may fail when you write your data, so you need to store your data in a way that you can recover from such a write or erase failure. So you can't just consider two bytes as a good integer for storing a value 0..65535.

EEPROM often supports 1 million write cycles and counted for single bytes or maybe small 16-byte sectors.

thanks for the reply Per.

I don't think that will be useful

because my 'frequently'= about 2000 per day.

and the data is 2 byte which is going to be updated.

thanks for your co operation...

It definitely added my knowledge...

because my 'frequently'= about 2000 per day.

and the data is 2 byte which is going to be updated.

how much flash do you have left?
how many years must your device function

with a 'walking write', you can get about a million writes (500 days) per 256 bytes of flash.

does your device give a 'power down interrupt?

Note that if counting every item to flash, then it isn't needed to store two bytes, i.e. 1878, 1879, 1880, 1881, ...

Each save would basically just be a +1, +1, +1, +1 in relation to a base counter value.

So a flash sector could contain:
1878, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4...
and unused bytes remains at 0xff. This means a 128 byte sector can spend maybe 4 bytes for initial value and inverse of initial value and then have room for 128-4 counts.

If the flash supports multiple writes of the single byte, then a 128-byte sector could fit 1000+ counts for a single erase cycle.

Then there exists processors that computes a CRC with every sector, setting the limit at one single write to a sector before it needs to be erased.

But if the hardware can't handle a dropping supply voltage correctly, then the firmware needs to be able to detect scrambled data and be able to figure out with a reasonably high safety margin how far it had made it before a flash write goofed and scrambled data. And that requires that there are some form of redundancy in the storage in the form of check bits or similar.

Checkpointed write transactions to non-volatile memory are used on some systems that lack adequate power-fail notification. A "record" is either written in its entirety before power fails or a partial write is "rolled back" during power-up recovery.

Some keywords to Google.