suppose i have 4MB of memory how divide data lines and address lines
You're an Embedded Engineer? Why wouldn't you know this?
Do you have a specific memory chip in mind? That would tend to solidify what your options are likely to be.
What is the width of the memory in question? This would drive the data bus width.
What is the type of memory in question? SRAM, DRAM, SDRAM? This along with the data width would drive the number of address bits required to describe 4MByte.
Are the buses multiplexed?
Looks like another consultant trying to recover themselves from saying they can do something that they know nothing about.