suppose i have 4MB of memory how divide data lines and address lines
You're an Embedded Engineer? Why wouldn't you know this?
Do you have a specific memory chip in mind? That would tend to solidify what your options are likely to be.
What is the width of the memory in question? This would drive the data bus width.
What is the type of memory in question? SRAM, DRAM, SDRAM? This along with the data width would drive the number of address bits required to describe 4MByte.
Are the buses multiplexed?
Looks like another consultant trying to recover themselves from saying they can do something that they know nothing about.
ijust have littel bit of confusion ..suppose 4gb of RAM Address lines are 32(2^32) and now how able get datalines?? how to it calculate??
Question regarding I2C Protocol &EEPROM: 1)how many device we are able connect in 7 bit address...119,112 or 128??why this restriction? 2)suppose I was connected five EEPROMs in a single master bus ..how can it enable those eeeprom's as a externally A2 A1 A0 pins or internal register A2 A1 A0 other wise both?? 3)in multi master I had 5 volts(it is fix I never decrease ) for one micro controller , 2nd micro controller is 4 volts and rest of the devices(slaves ) are 3 volts .how It can able to communicate together?? plz solve my question...