Hi guys,
I've just attempted to hash together some basic SPI test code, however, the module doesn't appear to be shifting data out to transmit. The Transmit Complete flag isn't triggering and my Logic Analyser isn't picking anything up on the relevant pins.
My code is as follows:
#define CMSIS_BITPOSITIONS 1 #include <LPC43xx.h> int main( void ) { // Update the System Core Clock SystemCoreClockUpdate(); // Configure pins for SPI LPC_SCU->SFSP3_6 = 1; // MISO LPC_SCU->SFSP3_7 = 1; // MOSI LPC_SCU->SFSP3_3 = 1; // SCK LPC_SCU->SFSP3_8 = 1; // SSEL // Configure the SPI Master Clock (PCLK_SPI / SPCCR) LPC_SPI->CCR = 16; // Configure the SPI Module for Master Mode LPC_SPI->CR |= SPI_CR_MSTR_Msk; while( 1 ) { LPC_SPI->DR = 0xA1; while( !(LPC_SPI->SR & SPI_SR_SPIF_Msk) ); } }
The unit appears to be powered, as I'm able to to set values in LPC_SPI->CR and LPC_SPI->CCR, however there's no evidence that data being inserted into LPC_SPI->DR is being shifted out.
I'm new to the 4357 and so perhaps I'm missing a step in clock setup? It's my understanding that SPI is enabled by default with a default base clock from the IRC.
Greatly appreciate any help, Many thanks
You should probably check your assumption for BASE_SPI_CLK, either by confirming the current value, or setting it explicitly.
I've just taken a look, all SPI clocks/gates appear to be active.
I've extended the code to the following but still no luck:
// Enable SPI and Peripheral Clocks LPC_CGU->BASE_SPI_CLK = ((0x00UL << CGU_BASE_SPIFI_CLK_PD_Pos) & CGU_BASE_SPIFI_CLK_PD_Msk) | // Enable Output Stage ((0x00UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) & CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk) | // Disable autoblocking ((0x01UL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) & CGU_BASE_SPIFI_CLK_CLK_SEL_Msk); // Clock Select (IRC) LPC_CGU->BASE_PERIPH_CLK = ((0x00UL << CGU_BASE_PERIPH_CLK_PD_Pos) & CGU_BASE_PERIPH_CLK_PD_Msk) | // Enable Output Stage ((0x00UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) & CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk) | // Disable autoblocking ((0x01UL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) & CGU_BASE_PERIPH_CLK_CLK_SEL_Msk); // Clock Select (IRC) LPC_CCU1->CLK_PERIPH_BUS_CFG = ((0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) & CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk) | // Enable Clock Run ((0x00UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) & CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk) | // Disable autoblocking ((0x00UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) & CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk); // Disable Wakeup LPC_CCU1->CLK_PERIPH_CORE_CFG = ((0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) & CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk) | // Enable Clock Run ((0x00UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) & CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk) | // Disable autoblocking ((0x00UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) & CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk); // Disable Wakeup LPC_CCU1->CLK_SPI_CFG = ((0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos) & CCU1_CLK_SPI_STAT_RUN_Msk) | // Enable Clock Run ((0x00UL << CCU1_CLK_SPI_STAT_AUTO_Pos) & CCU1_CLK_SPI_STAT_AUTO_Msk) | // Disable autoblocking ((0x00UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos) & CCU1_CLK_SPI_STAT_WAKEUP_Msk); // Disable Wakeup //LPC_RGU->RESET_CTRL0 // Configure pins for SPI LPC_SCU->SFSP3_6 |= 1; // MISO LPC_SCU->SFSP3_7 |= 1; // MOSI LPC_SCU->SFSP3_3 |= 1; // SCK LPC_SCU->SFSP3_8 |= 1; // SSEL // Configure the SPI Master Clock (PCLK_SPI / SPCCR) LPC_SPI->CCR = 16; // Configure the SPI Module for Master Mode and X LPC_SPI->CR |= SPI_CR_MSTR_Msk; while( 1 ) { LPC_SPI->DR = 0xA1; while( !(LPC_SPI->SR & SPI_SR_SPIF_Msk) ); } }
Hello,
i am dealing with exactly the same problem. Did you solve your problem? I would appreciate every help very much.
Kind regards,
Phil