I am using 8051F120 having 127KB Program memory, theoretically. I have written 4 *.C files residing in each bank. The length of the code in Bank1 and Bank2 is less than 32KB (observing the list file). But, instead of this, the linker gives an address space overflow for both the banks. Kindly assist.
Dhaval Solanki
But i still Fail to understand
The starting address of each bank = End address of common bank + 1
This should not happen, ideally.
On the contrary: that must happen. Your believing otherwise indicates you don't really understand how banking works.
The common bank is called a "common bank" because it contains the material that has to be commonly accessible to code in all banks. The only way that can work is if the entire address range of the common bank is reserved and kept available, regardless which other banks are mapped. In a scheme like SiLabs', with a 32KiB+32KiB hardwired bank mapping, the only way the common bank can become bigger than 32 KiB is if all bytes beyond the 32 KiB boundary are copied to all 3 "upper" banks, so they'll be accessible regardless which of the upper banks is currently active.
I think your real problem was that in your original configuration you placed too much stuff into the common bank yourself, causing this spill-over mechanism to be triggered.
Dear Hans-Bernhard Broeker, Thank you for clearing the air. But, in my opinion, there should be a document produced by the chip vendor stating this. A newbie may not understand this, the very first time he is using the IC, or may not have a clear picture unless he faces a problem like me.
Dhaval
But, in my opinion, there should be a document produced by the chip vendor stating this.
Though it might be helpful if the chip vendor produced application notes or other documentation relating to such things, I don't think it is really something that they should be expected to do. Which compiler vendors would they document for? Where would they stop?
The Keil documentation relating to banking is reasonably good and:
http://www.keil.com/support/man/docs/bl51/bl51_codebanking.htm
It just requires the reader to have an appreciation of what it is trying to achieve and what is possible.
But, in my opinion, there should be a document produced by the chip vendor stating this. well, SILabs does
The Keil documentation relating to banking is reasonably good and: but is somewhat invalid for the SILabs (and other?) chips with "internal banking"
go by the SILabs appnote, it is crystal clear
Erik
I'll take your word for it :)