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addition problem

Hi,

Recently I have come across a question on bits additions.
Maximum bits in register is 32 bits.
I want to perform 4 different 8 bit parallel additions in a single 32bits.
How do I actually detect, process the overflow and put into my result?

For example, {in hexadecimal}

In a loop,

R0 changes value after each loop, R1=#0 initially,

R1(new) is R1(old) + R0

when loop ends, I want to take into account of the overflow,

return R1 into 4 separate 8 bits for the sum. { R1=aabbccdd }

R1a= aa+overflow a
R1b= bb+overflow b
R1c= cc+overflow c
R1d= dd+overflow d

Thank you very much

Regards,
Pei

Parents
  • Keeping track of individual overflows is only possible if the processor has special SIMD instructions (single instruction multiple data) where the processor can see a single 32-bit register as two 16-bit numbers or 4 8-bit numbers. But even then, the processor would normally not support multiple add operations while retaining any multi-number carry values.

    A carry is normally just a single flag. It tells if the last operation did overflow or not. And this flag is then used as input parameter for an add-with-carry, that optionally adds in this carry bit when adding more significant parts of the number. But after that add-with-carry, the carry flag is once more regenerated.

    So carry flags can't handle a+b+c+d+e+f and then check if you got an overflow.

    Some DSP processors have special add instructions where you as input can have a 32-bit register containing four 8-bit numbers and as output get a 64-bit result containing four 16-bit values.

    This allows the DSP to loop through a vector of 8-bit quads and add them and get a result that has room for 256 add operations in a row before each individual sum may overflow.

Reply
  • Keeping track of individual overflows is only possible if the processor has special SIMD instructions (single instruction multiple data) where the processor can see a single 32-bit register as two 16-bit numbers or 4 8-bit numbers. But even then, the processor would normally not support multiple add operations while retaining any multi-number carry values.

    A carry is normally just a single flag. It tells if the last operation did overflow or not. And this flag is then used as input parameter for an add-with-carry, that optionally adds in this carry bit when adding more significant parts of the number. But after that add-with-carry, the carry flag is once more regenerated.

    So carry flags can't handle a+b+c+d+e+f and then check if you got an overflow.

    Some DSP processors have special add instructions where you as input can have a 32-bit register containing four 8-bit numbers and as output get a 64-bit result containing four 16-bit values.

    This allows the DSP to loop through a vector of 8-bit quads and add them and get a result that has room for 256 add operations in a row before each individual sum may overflow.

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