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Hello, I encounter issue using the aduc7020 in spi slave mode. I am implementing a spi driver in assembler by polling the SPISTA register status and with a clock parity and clockphase set to 1.
I do observe corrupted reading/writing and can t provide a confident result.
Is there any known limitation or bugs on the silicon of this chip?
Thank you
Indeed, at first sight on the scope , the signal are corrects: -For the clock, the polarity start high. - For the master, the bit is updating on the falling edge of the clock and the bit stay in the same states on the rising edge of the clock. I can read answer from my slave also. But there are not coherent. ( i ma just copying the received byte on the register RX on the TX register of the Aduc7020).
Based on this, if my master sends one byte for instance, the ADUC7020 should be able with 8 clock bits to receive this byte on the MOSI line and provides the same results on the MISO line.
Am i forgetting something?
I finnaly solve the issue. It was a bad grounding issue on my spi line