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Hello, I encounter issue using the aduc7020 in spi slave mode. I am implementing a spi driver in assembler by polling the SPISTA register status and with a clock parity and clockphase set to 1.
I do observe corrupted reading/writing and can t provide a confident result.
Is there any known limitation or bugs on the silicon of this chip?
Thank you
A SPI slave are normally never asynchronous. It needs a clock signal to the SPI logic that controls the internal state machine - among other things how often the signals should be polled.
This clock frequency must normally be a fixed number of times faster than the clock frequency used on the clock signal of the SPI bus.
So how fast do you run the SPI bus, and what clock frequency does that ADUC7020 have to run the internal SPI slave state machine?
Next thing is to make sure both sides agrees on phase and polarity of the clock signal - when they mismatch between master and slave, you get racing conditions where the transmitted signal changes just as the receiver samples the value.
Indeed, the master is configured with the same condition of clock polarity=1 and phase mode=1. I am using a 250Khz spi clock . A 40Mhz feeds the ADUC7020. But the result is not coherent with what is expected.
I have a SPICON register configured with the value 0x140d
And a main spi loop as : spiloop: stmdb r13!,{r0-r12,r14}
spistart_loop:
ldr r1,=0xFFFF0A00 /* read SPISTA */
ldr r2,=0xFFFF0A04 /* SPIRX */
ldr r3,=0xFFFF0A08 /*SPITX*/
wait_for_rx:
ldr r0,[r1] /*read SPISTA */
and r5,r0,#0x08 /* MASK with SPIRX register is full */
cmp r5,#0x08
beq rx_register_is_full
and r5,r0,#0x10
cmp r5,#0x10
b wait_for_rx
rx_register_is_full: ldr r4,[r2] /*read SPIRX */
str r4,[r3] /* copy the received byte in SPITX */
fill_tx_buffer: ldr r0,[r1] /* Get theSPISTA register */
and r5,r0,#0x1 /* wait the SPITX register is empty */
cmp r5,#0x1
beq fill_tx_buffer
b spistart_loop
ldmia r13!,{r0-r12,r14} bx lr
Don't rely on bits being zero or one. Different chips have different configurations to specify the polarity and phase. Have you verified (such as with an oscilloscope) that the master uses the phase and polarity you want it to? Have you verified (also with an oscilloscope) when the slave changes the state of the data line in relation to clock, and when it tristates the signal?
Indeed, at first sight on the scope , the signal are corrects: -For the clock, the polarity start high. - For the master, the bit is updating on the falling edge of the clock and the bit stay in the same states on the rising edge of the clock. I can read answer from my slave also. But there are not coherent. ( i ma just copying the received byte on the register RX on the TX register of the Aduc7020).
Based on this, if my master sends one byte for instance, the ADUC7020 should be able with 8 clock bits to receive this byte on the MOSI line and provides the same results on the MISO line.
Am i forgetting something?
I finnaly solve the issue. It was a bad grounding issue on my spi line