hello I am currently working on a project which has 20 Mhz osc. I am using LPC2368 I want CCLK should me 48Mhz Can anybody please explain me configuration required for pll registers. I have gone through NXP exel sheet according to that for my application M value is 12 N value is 1 Fcco value is 480
but when I make this changes I was not getting CCLK as 48MHz
Please Help!