Hi all
Hope someone can help me. I have some problems getting the EMC and SDRAM setup correctly. I think I may have something to do with the value loaded to the mode register!?
Basics: I'm using a LPC1788 at 120 MHz and the EMC clk is set to 120 MHz as well. I'm using Micron MT48LC8M16A2. It is a 16 bit 128 Mbit SDRAM. 4 banks. Using CAS 3 133 MHz is possible
Address Connections
LPC SDRAM A0 A0 A1 A0 .. .. .. .. A11 A11 A12 BA0 A13 BA1
See the init code i'm using below.
This is what I see:
32 bit writes: Value 0x11223344 written to base address. Also written the value to base address + 8 and base address + 12
Memory view: 44 33 22 11 00 00 00 00 44 33 22 11 44 33 22 11 00 00 0....
8 bit writes
Write value 0x11 at offset 0: 11 00 00 00 00 00 00 00 00 0..... <-- OK
Write value 0x22 at offset 1: 11 22 00 00 00 00 00 00 00 0..... <-- OK
Write value 0x33 at offset 2: 11 22 33 00 00 00 00 00 00 0..... <-- OK
Write value 0x44 at offset 3 33 44 33 44 00 00 00 11 22 33 44 33 44 33 44 00 00 0.... <-- Aggghhhhhh
Something seems to happen when the SDRAM is addressed if the high area?. I cant figure out what!!??
Is it OK using the A12 and A13 as BA0 and BA1 or must it be A13 and A14??
All help is appreciated
Best regards Thomas
EMC init code:
CLKPWR_SetCLKDiv(CLKPWR_CLKTYPE_EMC, 0x00000000); // 120 MHz EMC clk LPC_SC->PCONP |= 0x00000800; LPC_SC->EMCDLYCTL = 0x00001010; LPC_EMC->Control = 0x00000001; LPC_EMC->Config = 0x00000000; LPC_IOCON->P2_16 |= 0x201; // CAS LPC_IOCON->P2_17 |= 0x201; // RAS LPC_IOCON->P2_18 |= 0x201; // RAM clk LPC_IOCON->P2_20 |= 0x201; // DYSC0 LPC_IOCON->P2_24 |= 0x201; // CLKEN0 LPC_IOCON->P2_28 |= 0x201; // LDQM LPC_IOCON->P2_29 |= 0x201; // UDQM // D0-15 LPC_IOCON->P3_0 |= 0x201; LPC_IOCON->P3_1 |= 0x201; LPC_IOCON->P3_2 |= 0x201; LPC_IOCON->P3_3 |= 0x201; LPC_IOCON->P3_4 |= 0x201; LPC_IOCON->P3_5 |= 0x201; LPC_IOCON->P3_6 |= 0x201; LPC_IOCON->P3_7 |= 0x201; LPC_IOCON->P3_8 |= 0x201; LPC_IOCON->P3_9 |= 0x201; LPC_IOCON->P3_10 |= 0x201; LPC_IOCON->P3_11 |= 0x201; LPC_IOCON->P3_12 |= 0x201; LPC_IOCON->P3_13 |= 0x201; LPC_IOCON->P3_14 |= 0x201; LPC_IOCON->P3_15 |= 0x201; //A0-13 LPC_IOCON->P4_0 |= 0x201; LPC_IOCON->P4_1 |= 0x201; LPC_IOCON->P4_2 |= 0x201; LPC_IOCON->P4_3 |= 0x201; LPC_IOCON->P4_4 |= 0x201; LPC_IOCON->P4_5 |= 0x201; LPC_IOCON->P4_6 |= 0x201; LPC_IOCON->P4_7 |= 0x201; LPC_IOCON->P4_8 |= 0x201; LPC_IOCON->P4_9 |= 0x201; LPC_IOCON->P4_10 |= 0x201; LPC_IOCON->P4_11 |= 0x201; LPC_IOCON->P4_12 |= 0x201; // BA0 LPC_IOCON->P4_13 |= 0x201; // BA1 LPC_IOCON->P4_25 |= 0x201; // WE LPC_EMC->DynamicConfig0 = 0x00000480; /* 128B, 8Mx16, row=12, 4 banks, column=9 */ //Timing for 120MHz Bus: 8.333333 ns/clk LPC_EMC->DynamicRasCas0 = 0x00000303; // 3 RAS, 3 CAS latency */ //LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */ LPC_EMC->DynamicRP = 0x00000003; // Min 20ns. (n + 1) -> 3 clock cycles LPC_EMC->DynamicRAS = 0x00000006; // Min 44 ns.(n + 1) -> 6 clock cycles LPC_EMC->DynamicSREX = 0x0000000A; // Min 75 ns. ( n + 1 ) -> 10 clock cycles */ LPC_EMC->DynamicAPR = 0x00000005; // ??? ( n + 1 ) -> 2 clock cycles */ LPC_EMC->DynamicDAL = 0x00000006; // tWR + tRP: min 35 ns (n + 1) -> 5 clock cycles */ LPC_EMC->DynamicWR = 0x00000002; // Min 15 ns. ( n + 1 ) -> 2 clock cycles */ LPC_EMC->DynamicRC = 0x00000008; // Min 66 ns. ( n + 1 ) -> 8 clock cycles */ LPC_EMC->DynamicRFC = 0x00000008; // Min 66 ns. ( n + 1 ) -> 8 clock cycles */ LPC_EMC->DynamicXSR = 0x0000000A; // Min 75 ns. ( n + 1 ) -> 10 clock cycles */ LPC_EMC->DynamicRRD = 0x00000002; // Min 15 ns. ( n + 1 ) -> 2 clock cycles */ LPC_EMC->DynamicMRD = 0x00000002; // 2 tCK. ( n + 1 ) -> 2 clock cycles */ TIM_Waitms(100); /* wait 100ms */ LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */ TIM_Waitms(200); /* wait 200ms */ LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */ LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */ for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */ //Timing for 120MHz Bus LPC_EMC->DynamicRefresh = 0x2E; LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */ //Timing for 48/60/72MHZ Bus dwtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x33<<(13)))); /* 8 burst, 3 CAS latency */ LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */ //[re]enable buffers LPC_EMC->DynamicConfig0 |= 0x00080000; // Buffer enable TIM_Waitms(100);