I am trying to achieve a low latency PWM interrupt routine and cannot achieve fast register access times to any APB peripheral
using the document "Getting top performance from NXP's LPC processors", it provides timings for slow IO through the APB on the lpc214x for given APB dividers
divide 1, a store command will take 7 ticks (4 internal, 3 apb) divide 2, a store command will take 10 ticks (4 internal 6 apb) divide 4, a store command will take 16 ticks (4 internal 12 apb)
and likewise for fast IO when not using the APB a store command will take 2 ticks
I am trying to obtain APB timings on the lpc2468 and lpc2458 and expecting that I should be able to achieve something in the order of the lpc214x
I have performed the testing at both 72MHz and 12MHz, have all the ABP dividers excluding the RTC at /1 just incase the other peripherals affected the ABP
For the PWM, I am monitoring a PWM pin just to verify the PWM itself is fed with the 72MHz clock
PWM1MR0 = 0x00000002; /* Load prescaler */ PWM1MR5 = 0x00000001;
the output is 36MHz, so validated as running at 72MHz
I am using a simple assembler routine to ensure I have full control of the timing, and have reverted to using slow IO register access for easy scope access, which gives the same timing as the PWM register
EXPORT SBlink SBlink ldr r0,=0x01000000 ; pin 24 ldr r1,=0xe0028010 ; io1pin ; ldr r1,=0x3FFFC034 ; fio1pin SBlinkLoop str r0,[r1,#0x04] nop nop nop nop nop ; str r0,[r1,#0x0c] ;io str r0,[r1,#0x08] ;fio nop b SBlinkLoop
measuring just the +ve pulse, for the fast IO with SCS = 0x01, each nop takes 13.8nS and the str takes 28 or two cycles as per the referenced document
measuring just the +ve pulse, for the slow IO, each nop takes 13.8nS and the str takes 166nS or 12 cycles
the gpio divider is definately 1, providing 72MHz to GPIO. I have tried similar tests with the TMR, and PWM. all agree on the 12 cycle register access time
just in case the APB hardware is limited, the tests have been performed at a 12 MHz clock speed, and again the register access is 12 clock cycles
a further test at 72MHz with different GPIO dividers gives 16 clocks at /2 and 26 clocks at / 4, which
if the APB directly affects register access, so this possibly implies
/1 - 12 clocks : 7 internal + 5 apb /2 - 16 clocks : 6 internal + 10 apb /4 - 26 clocks : 6 internal + 20 apb
is there any definition of what access speed is available from the APB bus on the LPC2468/lpc2458, as it does not make sense that it is slower than the earlier device?
has anyone achieved or measured faster APB timings?
is there a register which defines the access speed of the actual ABP bus, and not just the peripheral?
just to keep things simple, I am using blinky.c, nothing else is running, no interrupt routine is running. all testing is performed on the MCB2460 evaluation card.