Hi,
I have a doubt related to 10-bit mode of I2C protocol:
As per I2C protocol, in a read or write transfer in 10-bit mode once a slave gets selected after receiving 2 bytes of address it remains addressed until it receives a STOP condition (P) or until it receives another repeated START condition (Sr) followed by a different slave address.
So, we have a possible format of transfer in which once a slave is selected with 2 bytes of address, it does not need complete address if it is to be selected again after a repeated start (Sr).
In 10-bit mode, more than one slave can give ACK for first byte of address as first address byte contains only two most significant bits of 10-bit slave address.
Now, consider a scenario in which we have two slaves with two most significant bits of address same. For such slaves first byte of address will be same as: First byte of address = 10-bit addressing code (5-bits) + 2 most significant bits of 10-bit slave address + 1 R/W bit
In this case, suppose we have a write transfer in which after start condition (S), master sends 2 address bytes and slave1 is selected and data transfer occurs. After any data byte and response, if repeated start (Sr) comes with first byte of address same as that in the previous transfer, then: Case 1: After a transfer with Slave 1 master wants to select it again 1) Slave 1 as well as Slave 2 will give ACK for the first address byte as it is same for both. 2) Master will enter into data phase as it wanted to select Slave 1 again so it will not send 2nd address byte. 3) After this, slave 1 will also enter into data phase as it remembers that it was selected in previous transfer and need not require 2nd address byte again. 4) But Slave 2 will enter into address phase for 2nd byte and since data phase is going on, Slave 2 will not receive its 2nd byte of address. So, it will give NACK and go in idle state.
- Invalid condition: But invalid condition can arise when first byte of data in this data phase (of master and Slave 1) will be equal to 2nd byte of address of Slave 2. In this condition both slaves will get selected in the same transfer.
Case 2: After a transfer with Slave 1 master wants to select Slave 2 1) Slave 1 as well as Slave 2 will give ACK for the first address byte as it is same for both. 2) After this, Master will send 2nd byte of address for Slave 2. 3) Slave 2 will give ACK for this 2nd byte of address. 4) As Slave 1 was selected in previous transfer, it will remember this and it will consider this 2nd byte as data.
- Invalid condition: So, an invalid condition arises in which both slaves get selected in the same transfer. Master is sending 2nd address byte, one slave is taking it as address byte but other slave is taking it as data byte.
The above described cases will arise in 10-bit mode read transfers also.
Please suggest me, if anyone has solution of this problem.
Thanks & Best Regards