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AT89S52

Dear Sir, I am having a problem with at89s52 on power up. I am doing a project which demands serial communication via serial port. I have gone through one of the threads here, where you had advised one Mr.Bhagirath to use 3-pin rest(MX810). So, I get it that the problem MAY BE in reset button. But, I would also like to share with you the fact that earlier I did not have any arrangement for reset, then it never misbehaved. So, what are the other areas from where this anomaly is rising?

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  • Hardly any processor can start receiving 8-bit data immediately on power up. The software normally have to set up baudrate etc for the UART to know what is expected.

    Another thing is the state of the line when the UART gets activated - a character that is sent before the UART is ready will be lost. So two processors can't be powered up and expected to be able to directly talk with each other. First off, there should be a bit of delay so both are in ready state before communication is activated. But the communication protocol should also support resends if it is important that no transfer is missing. How can one side ever know the other side is ready if there isn't hw or sw handshaking between them?

    But a correct reset solution is vital - lots of state in the processor that needs to be normalized. That also includes the interrupt state machines etc. Some of the states can't be corrected by the software.

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  • Hardly any processor can start receiving 8-bit data immediately on power up. The software normally have to set up baudrate etc for the UART to know what is expected.

    Another thing is the state of the line when the UART gets activated - a character that is sent before the UART is ready will be lost. So two processors can't be powered up and expected to be able to directly talk with each other. First off, there should be a bit of delay so both are in ready state before communication is activated. But the communication protocol should also support resends if it is important that no transfer is missing. How can one side ever know the other side is ready if there isn't hw or sw handshaking between them?

    But a correct reset solution is vital - lots of state in the processor that needs to be normalized. That also includes the interrupt state machines etc. Some of the states can't be corrected by the software.

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