We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi,
I am studying ARM's conditional execution code for my research. In my opinion, ARM condition codes and status registers is one of the greatest strengths of the processor.
I downloaded Keil uVision4 Evaluation Version and coded a simple C code I plucked from Wikipedia (en.wikipedia.org/.../ARM_architecture).
I then proceeded to compile the C code and switched to debug mode to study the asm code. However, instead of the optimized, more denser conditional codes, the codes are compiled into a "normal", non-optimized version.
For e.g. I am getting this:
CMP R2,R1 BLE 0x00000104 SUB R2,R2,R1 B 0x00000108 SUB R1,R1,R2 CMP R2,R1 BNE 0x000000F4
Instead of:
CMP Ri, Rj SUBGT Ri, Ri, Rj SUBLT Rj, Rj, Ri BNE loop
And this is my C code:
while(i != j) { if (i > j) i -= j; else j -= i; }
I am wondering if there is something wrong with my setting. I am looking for the most compact code possible especially on conditional execution.
Any type of help or advice is greatly appreciated.
HY