This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Suggesstions about TMS750LS20216

I have used LPC arm micros in my student project.
Now for my next project ( Model Rail )i want to use TMS750LS20216 TI micro.
I need suggestions from you peoples.

First one is support from vendor. I mean how much the vendor assist for their product i.e example code, tutorials, technical support team etc.

Second one, is hardware support of the selected device. Is there enough support for these devices form third party vendors? like debuggers/compilers etc.

You may say i should use google???
Yes used it and searched many things but in addition i need your experience about this device and its support.

Thanks in Advance!
Have a nice day!

Parents
  • I wasn't talking about switching who is master or slave. But the slave having the potential to tell the master to start sending null data if the master haven't anything meaningful to send. This allows the chips to enter sleep while any side may reactivate the SPI communication. The previous processor we used on the master side had the slave select input sharing pins with the second ethernet controller, making it impossible for it to be an SPI slave. But the system still needed either side to be able to activate full duplex communication. So A may stream data or commands to B and receive acknowledges back while B may stream data or commands to A while receiving acknowledges. So the master may say "activate output x" and get an acknowledge on that while at the same time the slave may say "here is the measurements from the analog inputs" and get an acknowledge on that. Or maybe a huge stream of incomming or outgoing CAN data.

Reply
  • I wasn't talking about switching who is master or slave. But the slave having the potential to tell the master to start sending null data if the master haven't anything meaningful to send. This allows the chips to enter sleep while any side may reactivate the SPI communication. The previous processor we used on the master side had the slave select input sharing pins with the second ethernet controller, making it impossible for it to be an SPI slave. But the system still needed either side to be able to activate full duplex communication. So A may stream data or commands to B and receive acknowledges back while B may stream data or commands to A while receiving acknowledges. So the master may say "activate output x" and get an acknowledge on that while at the same time the slave may say "here is the measurements from the analog inputs" and get an acknowledge on that. Or maybe a huge stream of incomming or outgoing CAN data.

Children
No data