I have used LPC arm micros in my student project. Now for my next project ( Model Rail )i want to use TMS750LS20216 TI micro. I need suggestions from you peoples.
First one is support from vendor. I mean how much the vendor assist for their product i.e example code, tutorials, technical support team etc.
Second one, is hardware support of the selected device. Is there enough support for these devices form third party vendors? like debuggers/compilers etc.
You may say i should use google??? Yes used it and searched many things but in addition i need your experience about this device and its support.
Thanks in Advance! Have a nice day!
You mean this: "
Does that really require a processor specifically designed for safety-critical systems?
"how much the vendor assist for their product i.e example code, tutorials, technical support team etc."
Have you actually looked on the TI website to see what they have available?
Have you looked at their support forums, to see the level of activity there?
I can certainly tell you that TI provide excellent support for their Stellaris range via their forums - they are one of the very few companies where the support staff do actively participate in the forum. [Keil et al take note!]
"Is there enough support for these devices form third party vendors? like debuggers/compilers etc."
That depends on what you mean by "enough" - doesn't it?
Again, the TI website should list 3rd-party support.
One thing to note, though, is that this chip is specifically targetted at safety-critical systems. That's a specialist market, which is bound to have less support than a "general purpose" product.
Also, safety-critical systems are, obviously, subject to stringent controls - so don't expect things to be "cheap" or "simple"
"Does that really require a processor specifically designed for safety-critical systems?"
It does, if the intention is to learn, using a model railway, how to create safety-critical systems. Few schools/companies can afford to have their own private full-scale railroad infrastructure just for teaching or for testing new designs ;)
"technical support team" Have you had large needs for any technical support with the NXP chips? Their manuals are normally quite good so people should be able to do almost everything without interacting with any technical support.
For special chips intended for very specific markets, the need for technical support may be much bigger. But the will to supply that support is greatly affected by the potential gain from giving it, i.e. if you are a potential customer interested in large quantities of their chips or if you are supplying solutions for any company who are a potential buyer of large quantities or if you are specifically educating developers involved with such a potential customer.
Most companies have questionable support unless they classify you as important and allows you to get in direct contact with the relevant engineers or at least forwards your questions to the relevant engineers.
en.wikipedia.org/.../Longmoor_Military_Railway
as you say, they couldn't affor to keep it going - so it closed in 1969.
Some NXP chips contain quite a few undocumented features...! :-)
Yes, I know. For example parameters to set up some memory controllers for specific memories don't have all the settings documented, so you have to get in contact with them and find out that they hardly know themselves what the parameters mean and what values they need to be set to.
The problems normally start when reaching the Linux-capable chips where NXP have probably bought complete modules to integrate with the core. So they don't really have the documentation or the knowledge what to do :(
Another recent example are the AHB bus arbitration settings that appeared out of the nowhere in the most recent user manual for the LPC2478 (and solved a flicker problem in one of our products!!!). Some peripherals sin too: LPC2400 SSP controller is capable of resetting its hardware buffer, so it seems. Is it documented? Ah, is the pope Jewish?!
Thanks to all for your kind information. Project is not a huge modle of rail. but it is designing of controlled rail including engine control,passangers safety, safe departure, safe arrival etc. Actually i have not started my project yet. This project is in scrach pad. i m searching for more info still....
Any way thanks a lot again. Have a nice day!
If the goal isn't to learn to develop for real human-safety standards, then I would consider using processors that are much used by lots of developers. NXP LPC23xx are much more common processors, which means you can get much more help from other people.
It's possible to implement code based on human-safety standards, even with chips that doesn't have any special hw support. Having two independent oscillators for example may not be needed for your model railroad. Or it could be solved with an external watchdog chip that requires you to drive a GPIO pin (with pulse or maybe even pattern) to acknowledge the program is running.
Special processors are best used when you have special needs. It isn't uncommon, when using chips that not too many uses, that there may be very troublesome errata for the chip, but the manufacturer don't have any reason to fix them as long as the general functionality can be accessed with more or less strange workarounds.
Right now, we have a project where we need to use two SPI controllers for a single link - the manufacturer of the chip have (oops) forgotten to add two DMA channels (receive and transmit concurrently) and same thing with FIFO. So one SPI device is master while the other SPI device is slave and listens to the answers from the other side. Strange workarounds needed because we needed a processor with some specific features that very few processors could supply. And the chip manufacturer for some reason didn't realize that SPI is duplex...
I second what Per says: the TMS750LS20216 is a specialist chip. By its very nature, that means that there will be a nuch smaller "community" than with any general purpose chip - so your chances of getting help & support will be much smaller.
Did you have some particular reason(s) not to continue using NXP's LPCxxxx chips?
Are there any particular chips that are "favourites" with the model rail "community"?
Is there any particular reason to do this on a microcontroller at all? Might it not be easier to do the application on a PC - possibly controlling a simple microcontroller just for IO interfacing?
Using a PC would certainly make the user interface nuch easier - and mimic diagrams, etc...
Should, of course, be: "a much smaller 'community'"
Per,
You posted
Right now, we have a project where we need to use two SPI controllers for a single link - the manufacturer of the chip have (oops) forgotten to add two DMA channels (receive and transmit concurrently) and same thing with FIFO. So one SPI device is master while the other SPI device is slave and listens to the answers from the other side.
I did something similar with two LPC2478s, but it was my choice - the SPI bus is used to deliver massive amounts of data, and we don't want the master to have to generate the clock cycles for the slave - therefore, we have opted for a half-duplex channel where only the MOSI line is used (DMA did not seem to help a lot to boost performance, alas). It does not matter really, as the protocol is rather simple - the sender packs the data (up to 1024 bytes) and the receiver only replies with a short ACK in between.
In our case, one side really is a duplex SPI. It's the other side that needs one master to send and one slave to receive because of a seriously broken silicon implementation.
A good SPI implementation should get hurt by having to generate the clock when data is only received. A simple solution is to run 16-bit words and have 0xffff reserved as NULL data. Then the receiving end can quickly scan FIFO or DMA data and ignore the NULL data with hardly any CPU load at all.
One trick to let the master rest when nothing needs to be sent in either direction is to have the slave side drive a signal (similar to a slave select) in reverse direction to an interrupt pin on the master. It activates this signal when it's in need of clocking to push data in the reverse direction.
Which processor are you referring to?
It activates this signal when it's in need of clocking to push data in the reverse direction.
Yes, we have 2 GPIO pins to arbitrate whose the master of the bus! It's actually a nice system, that I was able to build into a bootloader (one bootloader has a USB interface and sends binary images to another LPC2478, the other is only the client) and into the application, where the entire system is mirrored to accommodate data transfers to the other side as well. Pretty neat, but a little expensive in terms of computational power needed (hardware buffer is only 8 bytes long).