Arm7+transfer speed

Thanks for the mail.My application is to use lpc2368 and W5300. LPC2368 will receive 8 audio channel 32 bit data from FPGA at 96kbps (8*32*96k=24.576Mb/s=3.072MBytes/sec).Data at this rate has to be received , processed and sent to W5300.Will MCU which is running at 12.288MHz clock be able to take,process data to send to W5300(complete in 2 cycles)in synchronous with FPGA.W5300 which has network performance of 50Mbps and 8 independent sockets is obvious suitable to send data through Ethernet.
With Regards,
Lucky

Thanks for the mail.My application is to use lpc2368 and W5300. LPC2368 will receive 8 audio channel 32 bit data from FPGA at 96kbps (8*32*96k=24.576Mb/s=3.072MBytes/sec).Data at this rate has to be received , processed and sent to W5300.Will MCU which is running at 12.288MHz clock be able to take,process data to send to W5300(complete in 2 cycles)in synchronous with FPGA.W5300 which has network performance of 50Mbps and 8 independent sockets is obvious suitable to send data through Ethernet.
With Regards,
Lucky

96kbps is 96 kbits/second, which would mean 768kbits/s in total for 8 channels.

Do you mean kbps or did you mean kilosamples/second (kps)?

In your original post you talked about 72MHz ARM speed - now you suddenly seem to be talking about 12.288MHz.

Another thing - are you aware that the LPC2368 does have 100Mbit/s Ethernet support in the processor? What it needs is a PHY with RMII interface for the electrical interface.

Hi.Thanks for the reply.Data is 32 bit. so the rate is 24.576Mb/s.I am right in telling kbps.ARM7TDMI-S processor runs at up to 72 MHz.So,I mean to say lpc2368 can be swet to run up to run up to 72MHz.Clock i want to use is 12.288MHz for my appication.I want to know whether taking data at that rate and processing to send to W5300 will happen in two cycles?
With Regards,
Lucky

You are still mixing bits/second and samples/second.

They are only the same if the samples are one bit wide.

If you get 96 thousand samples / second and each sample is 32 bits large, then you get 96kps (kilosamples/second) and you get 6144kbit/s. Not any 96kbit/s.

And you still haven't commented why you want to use the W5300 for Ethernet, instead of using the internal Ethernet controller. And you haven't described how you intended to interface the W5300 with the processor. It seems to have an 8 or 16-bit wide memory interface - but the 2368 doesn't have any memory interface, except for use with serial memories. Did you intend to use GPIO?

By the way - why do you want to run the processor with 12.288MHz core speed? Note that it has internal baudrate generators so it doesn't need odd core speeds to get correct baudrates.

And you still haven't commented about your Ethernet stream - the need to get quick acknowledges on transmited data to be able to keep the transfer running without stalling. A PC that for some reason doesn't acknowledge received data means that you are quickly filling your RAM with new samples that can't be transmitted. What worst-case acknowledge times have you calculated for, on the receiving end? And what window size - number of concurrently outsdanding frames - did you plan for?

Hi,
As wiznet has got inbuilt Fully H/W Network protocol, we wanted to use it along with ARM7 though lpc series has internal Ethernet controller.

My application is as below. MCU receives 8 I2S signals which is at the rate of 96ksps,hence the rate 3.072MBytes/sec.We want to send through Ethernet using W5300.

With Regards,
Lucky

Now I ask directly: do you have a problem reading text?

The W5300 seems to have an parallell memory interface of 8 or 16 bit width for interfacing with a processor - signals described in chapter 1.3 of the datasheet. The 2368 doesn't have an external memory interface. Does the W5300 support any other interfacing method, or did you plan to use GPIO to interface it?

Do you think it is meaningful to consider if the LPC2368 is fast enough, if you continuously refuse to tell us what hardware interface on the LPC2368 you intend to use to interface with the W5300?

Next thing is that you in your last post talk about using I2S. - 8 I2S streams of 32-bit at 96kHz sampling rate. I know the LPC2368 can support 32-bit sample size. I know it can support stereo. I know it supports up to 96kHz sampling rate. But does it support 8 different such streams? Where in the user manual have you seen support for 8 channels?

Hi,
Sorry for not elaborating well. We want to use bit bang I2s using GPIO to receive 8 I2s streams as there is only 1 I2s interface in lpc2368We would like to use GPIO for interfacing with W5300.We took following link as a reference which has lpc2148 and w5300.
http://www.371.us/2148WZ.html
As I mentioned you as W5300 has hardwired tcp/ip stack, we wantto use it and will this combo able to send data through LAN at 3MBytes/sec.

"W5300 has hardwired tcp/ip stack, we wantto use it and will this combo able to send data through LAN at 3MBytes/sec"

But how fast can you feed the data to it ove a bit-banged GPIO interface?

Especially while you're also bit-banging eight I2S interfaces!

Have you noticed that the design that appears in the link you posted uses a LPC2148, which indeed does not have an Ethernet peripheral, but the LPC2368 does?!?

Especially while you're also bit-banging eight I2S interfaces!

Santa Maria.
Santa Clara.
Santa Barbara.
etc. etc. etc.

Now, how many posts did it take you to supply the information that you wanted to accelerate the Ethernet communication by manually generating address, data and clock signals, and that you wanted to bit-bang 8 separate I2S streams at 96*32=3072kHz speed?

Now, now many instructions does the processor need to perform one I2S transfer?
One for clock high.
One for clock low.
One for reading 8-bit data.
One for storing data.
One for incrementing target address (potentially incremented in prev instruction)
One for loop.

But say 6 instructions times 3072kHz = 18.423MHz. You wanted to run the CPU in 12.288MHz. See a problem.

Next thing. You need to produce output for the Ethernet controller. 6-10 instructions for every 2 bytes. And ou had 92ksps times 32 bytes so maybe 18-30 MIPS for that too.

Your available cycle count (at full 72MHz) is quickly running out. You still haven't included any main loop that makes decisions. Or interrupts. Or stalling waiting for flash reads. Or the killer - not all instructions can be issued one/cycle. Check the instruction timing for memory accesses...

The 2368 has two DMA channels. But not for random bitbanged input/output.

One for clock high.
One for clock low.
One for reading 8-bit data...

Surely, that process will need to be repeated for each bit on a bit-banged interface?

And the OP wants eight such interfaces...

And the OP wants eight such interfaces...

Of course. But you wouldn't run the 8 channels one at a time in sequence, would you?

One write can toggle the clock for all eight channels (one or eight pins depending on how the external hardware is connected).
One read can fetch one bit each from eight channels.
One more write to toggle the clock line again.

Obviously extra (tabulated) instructions are needed if the user wants to demultiplex the received channels, but to minimize the task for the microcontroller we assumes that we pick up the data with each bit in a byte representing one channel, and that we forward the data in the same way.