Arm7+transfer speed

Now, how many posts did it take you to supply the information that you wanted to accelerate the Ethernet communication by manually generating address, data and clock signals, and that you wanted to bit-bang 8 separate I2S streams at 96*32=3072kHz speed?

Now, now many instructions does the processor need to perform one I2S transfer?
One for clock high.
One for clock low.
One for reading 8-bit data.
One for storing data.
One for incrementing target address (potentially incremented in prev instruction)
One for loop.

But say 6 instructions times 3072kHz = 18.423MHz. You wanted to run the CPU in 12.288MHz. See a problem.

Next thing. You need to produce output for the Ethernet controller. 6-10 instructions for every 2 bytes. And ou had 92ksps times 32 bytes so maybe 18-30 MIPS for that too.

Your available cycle count (at full 72MHz) is quickly running out. You still haven't included any main loop that makes decisions. Or interrupts. Or stalling waiting for flash reads. Or the killer - not all instructions can be issued one/cycle. Check the instruction timing for memory accesses...

The 2368 has two DMA channels. But not for random bitbanged input/output.

Now, how many posts did it take you to supply the information that you wanted to accelerate the Ethernet communication by manually generating address, data and clock signals, and that you wanted to bit-bang 8 separate I2S streams at 96*32=3072kHz speed?

Now, now many instructions does the processor need to perform one I2S transfer?
One for clock high.
One for clock low.
One for reading 8-bit data.
One for storing data.
One for incrementing target address (potentially incremented in prev instruction)
One for loop.

But say 6 instructions times 3072kHz = 18.423MHz. You wanted to run the CPU in 12.288MHz. See a problem.

Next thing. You need to produce output for the Ethernet controller. 6-10 instructions for every 2 bytes. And ou had 92ksps times 32 bytes so maybe 18-30 MIPS for that too.

Your available cycle count (at full 72MHz) is quickly running out. You still haven't included any main loop that makes decisions. Or interrupts. Or stalling waiting for flash reads. Or the killer - not all instructions can be issued one/cycle. Check the instruction timing for memory accesses...

The 2368 has two DMA channels. But not for random bitbanged input/output.

One for clock high.
One for clock low.
One for reading 8-bit data...

Surely, that process will need to be repeated for each bit on a bit-banged interface?

And the OP wants eight such interfaces...

And the OP wants eight such interfaces...

Of course. But you wouldn't run the 8 channels one at a time in sequence, would you?

One write can toggle the clock for all eight channels (one or eight pins depending on how the external hardware is connected).
One read can fetch one bit each from eight channels.
One more write to toggle the clock line again.

Obviously extra (tabulated) instructions are needed if the user wants to demultiplex the received channels, but to minimize the task for the microcontroller we assumes that we pick up the data with each bit in a byte representing one channel, and that we forward the data in the same way.