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RTX with External SDRAM LPC1788 - causes bus fault

Hello,

I'm using the Embedded Artists LPC1788 development kit and I'm trying to get a very simple RTX application running using the external SDRAM.

Here is what I have so far:

1) A simple RTX application that runs (blinks an LED) with no problem when I use the internal RAM. This same application crashes with a bus fault in "os_sys_init" when I us the external SDRAM.

2) I configure and initialize the external SDRAM before the call to __main (this is working as I can run the same blinking LED using the SDRAM with no RTX.

3) Even if I let me STACK and HEAP remain in the internal RAM but have variables etc.. in the SDRAM I get the bus fault.

4) The bus fault is an IMPRECISERR: Imprecise data bus error

The call stack looks like this when the fault occurs:

HardFault_Handler -> rt_put_rdy_first() -> rt_dispatch() -> rt_task_create() -> SVC_Hanlder...

Does anyone have any suggestions? I see no reason why this should cause a fault.

Thanks.

MAC

Parents
  • Hi Dave,

    I noticed that in your macro:

    #define NS_2_CLKS(ns) ( (uint32_t)( (double)(ns) * tCLK_ns ) + 1 )   // convert ns to CCLKs
    

    you have "+ 1" is that correct? I thought that the + 1 happened in hardware.

    For example see table 118 from the user manual for DaynamicRP:

    Table 118. Dynamic Memory Precharge Command Period register (EMCDynamictRP - address 0x2009 C030) bit
    3:0 Precharge command
    period (tRP)
    0x0 -
    0xE
    n + 1 clock cycles. The delay is in EMCCLK cycles. 0x0F
    0xF 16 clock cycles (POR reset value).

    So if the datasheet says 18ns aren't you adding one extra clock cycle?

    I could just be missing something but this may actually explain why my setting aren't working.

    M

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  • Hi Dave,

    I noticed that in your macro:

    #define NS_2_CLKS(ns) ( (uint32_t)( (double)(ns) * tCLK_ns ) + 1 )   // convert ns to CCLKs
    

    you have "+ 1" is that correct? I thought that the + 1 happened in hardware.

    For example see table 118 from the user manual for DaynamicRP:

    Table 118. Dynamic Memory Precharge Command Period register (EMCDynamictRP - address 0x2009 C030) bit
    3:0 Precharge command
    period (tRP)
    0x0 -
    0xE
    n + 1 clock cycles. The delay is in EMCCLK cycles. 0x0F
    0xF 16 clock cycles (POR reset value).

    So if the datasheet says 18ns aren't you adding one extra clock cycle?

    I could just be missing something but this may actually explain why my setting aren't working.

    M

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