SSP peripheral + DMA

Thanks. So if I get it right, assuming my SSPx peripheral indicates the reception of 8 bytes (that number is fixed) by generating the proper interrupt, I collect these bytes into a small buffer in internal RAM, followed by a DMA transfer inside the SSP ISR to external RAM (where all the data of the peripheral is stored)? I though the peripheral takes control of the DMA independently...? So it boils down to memory to memory transfers - what's the point in peripheral to memory transfers then. I'm sorry, I'm a little confused...

Thanks. So if I get it right, assuming my SSPx peripheral indicates the reception of 8 bytes (that number is fixed) by generating the proper interrupt, I collect these bytes into a small buffer in internal RAM, followed by a DMA transfer inside the SSP ISR to external RAM (where all the data of the peripheral is stored)? I though the peripheral takes control of the DMA independently...? So it boils down to memory to memory transfers - what's the point in peripheral to memory transfers then. I'm sorry, I'm a little confused...

Or maybe you mean that once the SSP interrupt is in, I need to trigger a DMA transfers from the peripheral RAM to my external RAM buffer...? That sounds more likely!

You configure the DMA engine to know about what memory buffers to use for data.
You configure the DMA engine to connect to the SSP interface.

So when the SSP device is ready to send more data, the DMA engine can feed another word from memory buffers to keep the SSP constantly running. You either gives the DMA info about all the data to send and it sends it all and generates an interrupt when done. Or you keep updating the DMA engine with new buffers as the transfer progresses.

Same thing with incomming data. The DMA engine automatically moves bytes from the SSP to the specified buffer space in the speed the SSP is receiving them.

So there is no memory-to-memroy copy involved. Just memory to SSP or SSP to memory depending on the direction the DMA is confiured to operate. The DMA engine supports scatter or gather, by using linked lists. So when sending, it can walk a linked list to find memory regions (buffers) to use for transmission. When receiving, it can walk a linked list to find memory regions (buffers) to fill with received data.

Thank you - it is perfectly clear. I'm going to work on it - if I have more questions I will post them! Thanks again.

Per,

The SSP peripheral has a hardware buffer of 8 bytes. I can now generate a GPDMA interrupt based on it, and transfer the data to my buffer. The problem is that I did not manage to find in the user manual how it can determined what the actual transfer size was - one can configure the size of a transfer in the "GPDMA_CHx_CTRL" register, but it seems that the DMA interrupt is trigger only if the SSP peripheral has received at least that number of bytes - so if I make a transfer size 0x40 nothing happens, but anything less or equal to 8 does. I am missing here something!

It comes down to this: I am sending 14 bytes over the SSP bus. The first 8 arrive at the other end via DMA interrupt, but the remaining 6 are not - I only see one DMA interrupt, when the transfer size is 8.

In other words: is there a relation between the DMA transfer size parameter and the size of the hardware buffer of the SSP peripheral? Can the DMA start a transfer based on only one 1 arriving at the SSP even if the transfer size is significantly higher? It seems that it does not do that, and I don't understand why...!

Or: does the sender need to patch his data (with zeros, say), so that the DMA always detects 8 bytes in the hardware buffer of the SSP...?

I have found this in the user manual:

4.2.13 The completion of the DMA transfer indication
The completion of the DMA transfer is indicated by:
1. The transfer count reaching 0 if the GPDMA is performing flow control, OR
2. The peripheral setting the DMA Last Word Request Input (DMACLSREQ) or the DMA
Last Burst Request Input (DMALBREQ) if the peripheral is performing flow control.
According to Table 32–651 “DMA Connections”, SSP0, SSP1 and I2S do not use DMA
Last Word Request Input nor DMA Last Burst Request Input. Therefore there will be no
indication of completion if SSP0, SSP1 and I2S are performing the flow control.

does this mean that when SSP1 is coupled to DMA (which must do the flow control, according to paragraph 2), the DMA cannot try to transfer more than the hardware buffer size of SSP (8 bytes) per transfer?

I am sending 16 bytes into the SSP peripheral. I _always_ have the first 8 bytes transferred via DMA to the right place, but the next 8 bytes are not!
Does anybody have any idea what might cause this?