The SSP peripheral of my LPC2478 (configured to use SPI frames) is generating a "RNE equals 1" status (Receiver Not Empty - thus, there is data available in the RX FIFO) after some data is placed in the data register to be sent out (I am sure no data has actually been received from the slave). I cannot find an explanation for this - however, I must add that I am using a temporary test rig (until the real hardware is available) that might suffer from EMC issues, and that if I slowly run the code using a debugger this does not seem to occur. I did not find any indication in the user manual that such behavior can be expected, but some guy at NXP told me that "When the transmission is over, it is expected that the receive channel also contains data. " (there has been no further advise from them). Does this make sense to you? All in all it is working, and I can sustain a transfer rate of over 36 KB/sec in a (still) non-preemptive environment, but this does not seem right, so I was hoping you can share your thoughts with me.
Thanks Per. In the system I'm working on now, each peer that wants to send data takes the role of the SPI bus master (don't worry: there is role arbitration using 2 GPIO pins), so that I don't have to generate the clock pulses for the slave by dummy writes/reads at the master - replies could be quite long and that is not possible to sustain in a preemptive environment anyway (unless you really jump through the hoops!). So there a data transfer protocol underneath which dictates who the physical bus master actually is (a role that is exchanged between the peers), but the "logical master" does not - the logical master is the peer that initiated the entire transaction (the logical slave can only reply with a NACK or ACK). This may be slightly limited by greatly simplifies the protocol.