CortexM0 Multiple SvcHandlers

Why not just disable interrupts around that code?

What if then just on that moment another IRQ arravices ?

I am not familiar with ASM ASM code

In the SVC_handler i should setup a table with vectors for my soft irq routines
the requested handler to executes index is in one of the registers. thats al i could figure out.

but i dont know how to do this in assembler
must be a relative jump in this table.

it must be similar like the swi.s from the lpc21xx ARM7 , nut this is cortex M0 and seems be somewhat different.

Johan

"What if then just on that moment another IRQ arrives ?"

Sorry - I don't get you?

You disable interrupts immediately before your critical code starts; so, when your critical code is running, interrutps are disabled - therefore, your code cannot be interrupted!

QEF?

hi
I dont want to disable the interrupts, here is how it worked on lpc 21xx
in my main i simmply called swi_kick_wd ();
The problem is that the assembly code part from lpc21xx does not work for the cortex M0 and i don't know how to change the assemby languase to make it work.
The SCC call makes it possible to onse 256 different software interrupt handlers.

///////////// C code part
/* * Software Interrupt Function accept parameters and run in * Supervisor Mode (Interrupt protected) */

void __swi(0) swi_kick_wd (void);
void __SWI_0 (void)
{ WDFEED=0xaa; WDFEED=0x55;
}

void __swi(1) set_io0(unsigned int mask,unsigned int data);
void __SWI_1 (unsigned int mask,unsigned int pindata)
{ FIOMASK=mask; FIOPIN=pindata;
}

unsigned int __swi(2) get_io0(unsigned int mask);
unsigned int __SWI_2 (unsigned int mask)
{ FIOMASK=mask; return FIOPIN;
}

void __swi(3)setbuzzer(int state);
void __SWI_3 ( int var)
{ if (var) { FIO0MASK3=0xfd; FIO0PIN3 =0x02; } else { FIO0MASK3=0xfd; FIO0PIN3 =0x00; }
}

//assembly code part :

;/*****************************************************************************/
;/* SWI.S: SWI Handler */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/

T_Bit EQU 0x20

PRESERVE8 ; 8-Byte aligned Stack AREA SWI_Area, CODE, READONLY ARM

EXPORT SWI_Handler
SWI_Handler

STMFD SP!, {R12, LR} ; Store R12, LR MRS R12, SPSR ; Get SPSR STMFD SP!, {R8, R12} ; Store R8, SPSR TST R12, #T_Bit ; Check Thumb Bit LDRNEH R12, [LR,#-2] ; Thumb: Load Halfword BICNE R12, R12, #0xFF00 ; Extract SWI Number LDREQ R12, [LR,#-4] ; ARM: Load Word BICEQ R12, R12, #0xFF000000 ; Extract SWI Number

LDR R8, SWI_Count CMP R12, R8 BHS SWI_Dead ; Overflow ADR R8, SWI_Table LDR R12, [R8,R12,LSL #2] ; Load SWI Function Address MOV LR, PC ; Return Address BX R12 ; Call SWI Function

LDMFD SP!, {R8, R12} ; Load R8, SPSR MSR SPSR_cxsf, R12 ; Set SPSR LDMFD SP!, {R12, PC}^ ; Restore R12 and Return

SWI_Dead B SWI_Dead ; None Existing SWI

SWI_Cnt EQU (SWI_End-SWI_Table)/4
SWI_Count DCD SWI_Cnt

IMPORT __SWI_0 IMPORT __SWI_1 IMPORT __SWI_2 IMPORT __SWI_3
SWI_Table DCD __SWI_0 ; SWI 0 Function Entry DCD __SWI_1 ; SWI 1 Function Entry DCD __SWI_2 ; SWI 2 Function Entry DCD __SWI_3 ; SWI 3 Function Entry
; ...
SWI_End

END

> I dont want to disable the interrupts, here is how it worked on lpc 21xx

Sure, but why not? The effect of using an SVC (formerly known as SWI) to prevent interrupts from becoming active is no different from disabling them. In fact, the latter is a lot easier to program and likely more efficient (both, size and performance).

Regards
Marcus
http://www.doulos.com/arm/

PS: Please use proper tags if you post code

But why not?

Of course, you may have a (very) good reason - in which case, you should be able to explain it.

Without knowing why you're doing something, it is impossible for people to know whether or not suggestions are appropriate to your situation.

And it might be that you really don't need to do it this way - and there are (much) better ways to do it...

Remember: nobody knows anything about you or your project other than what you explicitly state in your posts!

Also, please note the instructions on how to post source code:

www.danlhenry.com/.../keil_code.png

It is quite easy to believe that if you turn off interrupts, your processor will not detect interrupts. It still does.

Next thing that is easy to believe is that if you turn off interrupts, you get more latencies and jitter. But when you play with your SWI(0) handler, you set the processor in a mode that has higher priority than your normal interrupts. So they will be just as disabled as if you had turned off interrupts the direct way.

So in the end, you have two similar ways to block interrupts while you perform your critical section.

So make sure you know the reasons for doing it one thing instead of some other way.

Are there no unwanted side effects when disabling interrupts from within an isr ?

I am not 100% sure, but in my '8051' period, turning off irqs could lead to missed irq's.

Johan