Hello
I m trying to initialise a MT48LC2M32B2 SDRAM coming from MICRON with a LPC3250. Here is my function:
void initSDRAM() { int dummy = dummy; SDRAMCLK_CTRL = 0x0; //validation SDRAM HCLK MPMCAHBControl0 = 0x1; MPMCAHBControl2 = 0x1; MPMCAHBControl3 = 0x1; MPMCAHBControl4 = 0x1; MPMCAHBTimeout0 = 0x0100; MPMCAHBTimeout2 = 0x0190; MPMCAHBTimeout3 = 0x0190; MPMCAHBTimeout4 = 0x0190; SDRAMCLK_CTRL = 0x72800; //slow slewrate for 2V8 IO and 2.5ns delay MPMCControl = 0x1; // validation EMC MPMCConfig = 0x0; // little endian mode MPMCDynamicConfig0 = 0x00004300; // 64MB, 2Mbx32, 4 banks, row=11, column=8 MPMCDynamicRasCas0 = 0x00000303; // Default setting, RAS latency 3 CCLKs, CAS latenty 3 CCLKs. MPMCDynamicReadConfig = 0x11; // Command delayed strategy MPMCDynamicRP = 2; // command period: 3(n+1) clock cycles MPMCDynamicRAS = 3; // RAS command period: 4(n+1) clock cycles MPMCDynamicSREX = 7; // Self-refresh period: 8(n+1) clock cycles MPMCDynamicWR = 1; // Write recovery: 2(n+1) clock cycles MPMCDynamicRC = 7; // Active to Active cmd: 8(n+1) clock cycles MPMCDynamicRFC = 7; // Auto-refresh: 8(n+1) clock cycles MPMCDynamicXSR = 7; // Exit self-refresh: 8(n+1) clock cycles MPMCDynamicRRD = 1; // Active bank A->B: 2(n+1) clock cycles //ini : 2 MPMCDynamicMRD = 2; // Load Mode to Active cmd: 3(n+1) clock cycles MPMCDynamicCDLR = 1; MPMCDynamicRefresh = 50; //50 x 16CCLKs=800CCLK=7us between SDRAM refresh cycles wait(1); //envoi d'un NOP MPMCDynamicControl = 0x00000193; wait(20); //delai de 100us mini // envoi d'un PRECHARGE MPMCDynamicControl = 0x00000113; MPMCDynamicRefresh = 8; wait(1); MPMCDynamicRefresh = 50; //50 x 16CCLKs=800CCLK=7us between SDRAM refresh cycles wait(1); MPMCDynamicControl = 0x00000093; // envoi de la commande de programmation du MODE REGISTER dummy = *((volatile int *)(SDRAM_BASE_ADDR | (0x33 << 12))); //send NOP MPMCDynamicControl = 0x00000193; // Send command: NORMAL MPMCDynamicControl = 0x00000001; //0x01 because code is in NOR FLASH wait(20); // 1 = 10 us }
After this was executed, I can see the refresh of the SDRAM. But unfortunately, when I write something, I can t read it, even if in the debugger. The frequency of the HCLK is 104 MHz, the same as the EMC clk. Can someone help me with this problem? Thanks in advance
Best Regards Yuga
I do. The code I write come from the Phytec example. On the evaluation board, the code for the initialization SDRAM and my code for test works great (but it s not the same size and voltage of SDRAM). When I change the parameters for my SDRAM, there is any response of it. Therefore I post here.
Thanks in advance Yuga
There is no simple solution to your problem, you have to analyze datasheet for memory that you are using and implement manufacturers initialization routine exactly. Usually the problem is in delays needed in initialization routine perhaps they are not as requested by manufacturer. Also you can try to find some source code for initializing these chips and analyze it.