We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi, I have a problem with my STR9 when I try to use USB library (VirtualCOM) and RTX at the same time. I'm starting from 2 projects running well: the first one uses RTX (Blinky_RTX is a Keil example) and the second one opens a VirtualCOM. The problem occurs when i try to merge them: if I add the RTX on the VirtualCOM project, the micro does not start the operative system. I think the problem is in the sturt-up code but I don't know how to resolve it... Can someone help me??
Thanks in advance
Now the big question.
Did you repost your source code, or did you copy the already failed posts and posted once more?
Look for example at:
IRQHandler SUB lr,lr ,#4 SaveContext r0,r3 LDR r0, = VectorAddress LDR r0, [r0] ; Read the routine address from VIC0 Vector Address register
Do your original source file contains multiple assembler instructions on the same text line?
Notice the button "Preview" that you have to press as first step when posting source code. Did you remember to preview?
Now, you have posted the code twice. And both copies are unreadable.
I'm sorry, I hope now is fine
Debug_Mode EQU 0 (I & F) flags in PSRs Mode_USR EQU 0x10 Mode_FIQ EQU 0x11 Mode_IRQ EQU 0x12 Mode_SVC EQU 0x13 Mode_ABT EQU 0x17 Mode_UND EQU 0x1B Mode_SYS EQU 0x1F I_Bit EQU 0x80 F_Bit EQU 0x40 UND_Stack_Size EQU 0x00000000 SVC_Stack_Size EQU 0x00000008 ABT_Stack_Size EQU 0x00000000 FIQ_Stack_Size EQU 0x00000020 IRQ_Stack_Size EQU 0x00000100 USR_Stack_Size EQU 0x00000400 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE USR_Stack_Size __initial_sp SPACE ISR_Stack_Size Stack_Top Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset FMI_BASE_Address EQU 0x54000000 FMI_BBSR_OFST EQU 0x00000000 FMI_NBBSR_OFST EQU 0x00000004 FMI_BBADR_OFST EQU 0x0000000C FMI_NBBADR_OFST EQU 0x00000010 FMI_CR_OFST EQU 0x00000018 FMI_SETUP EQU 1 FMI_CR_Val EQU 0x00000018 FMI_BBSR_Val EQU 0x00000004 FMI_BBADR_Val EQU 0x00000000 FMI_NBBSR_Val EQU 0x00000002 FMI_NBBADR_Val EQU 0x00080000 FLASH_CFG_Val EQU 0x00000000 PRESERVE8 AREA Init, CODE, READONLY ARM EXPORT Reset_Handler Reset_Handler LDR pc, =NextInst NextInst IF Debug_Mode=1 MOV r0, #0x4000 Loop SUBS r0,r0, #1 SUBS r0,r0, #1 SUBS r0,r0, #1 SUBS r0,r0, #1 SUBS r0,r0, #1 SUBS r0,r0, #1 SUBS r0,r0, #1 SUBS r0,r0, #1 BNE Loop ENDIF MRC p15, 0, r0, c1, c0, 0 ORR r0, r0, #0x8 MCR p15, 0, r0, c1, c0, 0 MOV r0, #0x40000 MCR p15,0x1,r0,c15,c1,0 ;------------------------------------------------------------------------------ ; Description : FMI Registers configuration depending on the Flash size selected, ; and the boot bank. ; ; After reset, the application program has to write the size and start ; address of Bank 1 in the FMI_BBSR and FMI_BBADR registers and the size and ; start address of Bank 0 in the FMI_NBBSR and FMI_NBBADR registers. ; ------------------------------------------------------------------------------ LDR R6, =FMI_BASE_Address LDR R7, = FMI_BBSR_Val ; BOOT BANK Size= STR R7, [R6, #FMI_BBSR_OFST] ; (2^BOOT_BANK_Size) * 32KBytes LDR R7, = FMI_NBBSR_Val ; NON BOOT BANK Size = STR R7, [R6, #FMI_NBBSR_OFST] ; (2^NON_BOOT_BANK_Size) * 8KBytes LDR R7, =FMI_BBADR_Val ; BOOT BANK Address MOV R7, R7 ,LSR #0x2 STR R7, [R6, #FMI_BBADR_OFST] LDR R7, =FMI_NBBADR_Val ; BOOT BANK Address MOV R7, R7 ,LSR #0x2 STR R7, [R6, #FMI_NBBADR_OFST] LDR R7, = 0x19 ; Enable Both banks STR R7, [R6, #FMI_CR_OFST] ; --- Enable 96K of RAM & Disable DTCM & AHB wait-states LDR R0, = SCU_BASE_Address LDR R1, = 0x0191 STR R1, [R0, #SCU_SCR0_OFST] ; Setup Stack for each mode LDR R0, =Stack_Top ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size ; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_SYS IF :DEF:__MICROLIB EXPORT __initial_sp ELSE MOV SP, R0 SUB SL, SP, #USR_Stack_Size ENDIF ; Enter the C code IMPORT __main B __main IF :DEF:__MICROLIB EXPORT __heap_base EXPORT __heap_limit ELSE ; User Initial Stack & Heap AREA |.text|, CODE, READONLY IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + USR_Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ENDIF END
VectorAddress EQU 0xFFFFF030 EXPORT Vectors IMPORT Reset_Handler IMPORT Undefined_Handler IMPORT SWI_Handler IMPORT Prefetch_Handler IMPORT Abort_Handler IMPORT FIQ_Handler RESERVE8 AREA Reset, CODE, READONLY ARM Vectors LDR PC, Reset_Addr LDR PC, Undefined_Addr LDR PC, SWI_Addr LDR PC, Prefetch_Addr LDR PC, Abort_Addr NOP LDR PC, IRQ_Addr FIQHandler SUB lr,lr,#4 STMFD sp!,{r0-r3,lr} ldr r0,=FIQ_Handler ldr lr,=FIQ_Handler_end bx r0 FIQ_Handler_end LDMFD sp!,{r0-r3,pc}^ ;******************************************************************************* ; Exception handlers address table ;******************************************************************************* Reset_Addr DCD Reset_Handler Undefined_Addr DCD UndefinedHandler SWI_Addr DCD SWIHandler Prefetch_Addr DCD PrefetchAbortHandler Abort_Addr DCD DataAbortHandler DCD 0 IRQ_Addr DCD IRQHandler MACRO SaveContext $reg1,$reg2 STMFD sp!,{$reg1-$reg2,lr} MEND MACRO RestoreContext $reg1,$reg2 LDMFD sp!,{$reg1-$reg2,pc}^ MEND ;******************************************************************************* ; Exception Handlers ;******************************************************************************* UndefinedHandler SaveContext r0,r3 ldr r0,=Undefined_Handler ldr lr,=Undefined_Handler_end bx r0 Undefined_Handler_end RestoreContext r0,r3 ;******************************************************************************* ;* Function Name : SWIHandler ;* Description : This function is called when SWI instruction executed. ;* Input : none ;* Output : none ;******************************************************************************* SWIHandler SaveContext r0,r3 ldr r0,=SWI_Handler ldr lr,=SWI_Handler_end bx r0 SWI_Handler_end RestoreContextr0,r3 ;******************************************************************************* ;* Function Name : PrefetchAbortHandler ;* Description : This function is called when Prefetch Abort ; exception is entered. ;* Input : none ;* Output : none ;******************************************************************************* PrefetchAbortHandler SUB lr,lr,#4 SaveContext r0,r3 ldr r0,=Prefetch_Handler ldr lr,=Prefetch_Handler_end bx r0 Prefetch_Handler_end RestoreContext r0,r3 ;******************************************************************************* ;* Function Name : DataAbortHandler ;* Description : This function is called when Data Abort ; exception is entered. ;* Input : none ;* Output : none ;******************************************************************************* DataAbortHandler SUB lr,lr,#8 SaveContext r0,r3 ldr r0,=Abort_Handler ldr lr,=Abort_Handler_end bx r0 Abort_Handler_end RestoreContext r0,r3 ;******************************************************************************* ;* Function Name : IRQHandler ;* Description : This function is called when IRQ exception is entered. ;* Input : none ;* Output : none ;******************************************************************************* IRQHandler SUB lr,lr ,#4 SaveContext r0,r3 LDR r0, = VectorAddress LDR r0, [r0] BLX r0 RestoreContext r0,r3 LTORG END