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Hi All,
I need to bring up a Keil PK51 subsystem platform that contains the following needs:
Two IP core DP8051 CPU’s share same 64k RAM code and 16M data. CPU A run a boot loader and application A CPU B run application B.
Sequence of operation: CPU B is halted CPU A boot loader loads code from E2prom to 64k ram (0-32K for cpu A, 32-64K for cpu B ). CPU A application A starts its operation from 0-32K. CPU A application releases CPU B from reset. CPU B address 0 is HW trapped to jump to address 32K were application B was loaded. CPU B application B starts its operation from 32K-64K. Both cpu running.
Data segment: Both CPU A and CPU B are operating on data segment of 16M, each one writes/reads different register in the same data space.
How do you think I should build it in the Keil environment?
Thanks,
Most definitely preferable to remap the address space so both cores thinks the code space starts from address zero. The boot loader should be able to remap the address space after having copied the program from EEPROM.
And the design must support concurrent access to the memory. If the memory doesn't support at least twice the bandwidth that the cores may require (allowing the cores to access memory on odd/even phase) then the cores must have support to handshake for the memory accesses so that they get extra waitstates until the memory is ready.