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Hi All,
I need to bring up a Keil PK51 subsystem platform that contains the following needs:
Two IP core DP8051 CPU’s share same 64k RAM code and 16M data. CPU A run a boot loader and application A CPU B run application B.
Sequence of operation: CPU B is halted CPU A boot loader loads code from E2prom to 64k ram (0-32K for cpu A, 32-64K for cpu B ). CPU A application A starts its operation from 0-32K. CPU A application releases CPU B from reset. CPU B address 0 is HW trapped to jump to address 32K were application B was loaded. CPU B application B starts its operation from 32K-64K. Both cpu running.
Data segment: Both CPU A and CPU B are operating on data segment of 16M, each one writes/reads different register in the same data space.
How do you think I should build it in the Keil environment?
Thanks,
Why do you want to share the same RAM?
How are you going to implement the memory interface so that the RAM is ready to perform memory accesses to both processors?
How will you protect the memory when one processor needs to do a multi-byte write while the other processor needs to do a read?
Is shared memory a requirement to be able to run two processor cores in the same chip?
Hi, The share RAM is mapped up to 16M. It contains variable and HW register space. Both CPU use the same bus but access different address in the far 16M memory. The bus will allow each time a different CPU to use the RAM. From software point of view I have two CPU’s running different code and RAM spaces. How it’s best to implement it?
Two IP core DP8051 CPU’s share same 64k RAM code and 16M data
sure you can have different address ranges except for the vector space but how do you propose tho 'share' the read and write pins on the memory.
Erik
By using a HW MUX
what controls the mux? most (all I know) such systems get in big doo-doo if both processors request access within the same picosecond. I have worked with this (inherited system) and, till everything was redone to get rid of this scheme, had to live with one failure per day per 1000 units.
also, how do you handle the "high memory" processors vectors in the same place as the "low memory" processors. ?
Hi,
What do you refer by: handle the "high memory" processors vectors in the same place as the "low memory"
Each has its own SFR, stack .. Both share the same 16M RAM xdata/far space.
But where do the two processors store their interrupt vector table when you have a shared code memory for them?
not SFRs
The interrupts of CPUB can be located at differnt address space then 0, for example 32K.
The interrupts of CPUB can be located at differnt address space then 0, for example 32K how
CPU B address 0 is HW trapped to jump to address 32K were application B was loaded. CPU B application B starts its operation from 32K-64K.
I don't see how that part of your plan makes sense. Mapping those 32KB into the address space of CPU B as 0..32K would be a whole lot more transparent than that.
Most definitely preferable to remap the address space so both cores thinks the code space starts from address zero. The boot loader should be able to remap the address space after having copied the program from EEPROM.
And the design must support concurrent access to the memory. If the memory doesn't support at least twice the bandwidth that the cores may require (allowing the cores to access memory on odd/even phase) then the cores must have support to handshake for the memory accesses so that they get extra waitstates until the memory is ready.