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Hi All,
I need to bring up a Keil PK51 subsystem platform that contains the following needs:
Two IP core DP8051 CPU’s share same 64k RAM code and 16M data. CPU A run a boot loader and application A CPU B run application B.
Sequence of operation: CPU B is halted CPU A boot loader loads code from E2prom to 64k ram (0-32K for cpu A, 32-64K for cpu B ). CPU A application A starts its operation from 0-32K. CPU A application releases CPU B from reset. CPU B address 0 is HW trapped to jump to address 32K were application B was loaded. CPU B application B starts its operation from 32K-64K. Both cpu running.
Data segment: Both CPU A and CPU B are operating on data segment of 16M, each one writes/reads different register in the same data space.
How do you think I should build it in the Keil environment?
Thanks,
what controls the mux? most (all I know) such systems get in big doo-doo if both processors request access within the same picosecond. I have worked with this (inherited system) and, till everything was redone to get rid of this scheme, had to live with one failure per day per 1000 units.
also, how do you handle the "high memory" processors vectors in the same place as the "low memory" processors. ?
Erik
Hi,
What do you refer by: handle the "high memory" processors vectors in the same place as the "low memory"
Each has its own SFR, stack .. Both share the same 16M RAM xdata/far space.
But where do the two processors store their interrupt vector table when you have a shared code memory for them?
not SFRs
The interrupts of CPUB can be located at differnt address space then 0, for example 32K.
The interrupts of CPUB can be located at differnt address space then 0, for example 32K how