Hi,
I wish to improve performances of my application by enabling I and D cache in my LPC3131 chip.
I don't use any external memories and no OS.
One says me : "The default MMU tables in BootROM map ISRAM area 0x11028000 as non-cacheable areas. But the same ISRAM are is mapped at virtual memory 0x11128000 as cacheable & bufferable. So if you compile your code with base address as 0x11129000 you should be able to use ARM caches. But you should make sure you take care of cache coherency issues."
I found the value 0x11028000 in the file lpc313x_chip.h in two locations : ISRAM_BASE and ISRAM_ESRAM0_BASE I change it to 0x11128000
I found the value 0x11029000 in the files : keil_init.h and ea3131_startup_entry. In both files I change to 0x11129000
Finally I change compilation option to match this new memory layout.
However my application does not work anymore with those changes. Does anyone have an idea on how to enable ARM caches properly?
Best regards