Hi,
I wish to improve performances of my application by enabling I and D cache in my LPC3131 chip.
I don't use any external memories and no OS.
One says me : "The default MMU tables in BootROM map ISRAM area 0x11028000 as non-cacheable areas. But the same ISRAM are is mapped at virtual memory 0x11128000 as cacheable & bufferable. So if you compile your code with base address as 0x11129000 you should be able to use ARM caches. But you should make sure you take care of cache coherency issues."
I found the value 0x11028000 in the file lpc313x_chip.h in two locations : ISRAM_BASE and ISRAM_ESRAM0_BASE I change it to 0x11128000
I found the value 0x11029000 in the files : keil_init.h and ea3131_startup_entry. In both files I change to 0x11129000
Finally I change compilation option to match this new memory layout.
However my application does not work anymore with those changes. Does anyone have an idea on how to enable ARM caches properly?
Best regards
Keil example for Embedded Artists LPC3131 board (can be found in folder Keil\ARM\Boards\Embedded Artists\LPC3131) has procedure for enabling instruction cache in startup, for Data cache you will have to look at ARM9 core documentation on how to use it.
Thanks a lot, I need to update my version of ARM MDK to have the blinky example with I-cache enabled.
So don't I need to deal with MMU Table ?
I will look further for D-cache usage, but I think my application will not benefit of D-cache.
If you just need instruction cache then blinky will be enough, for data cache there is some work to be done, and if you don't need it then Blinky is all you need.
Maybe see the below link.
RE: How to use MMU? by Marcus Harnisch http://www.keil.com/forum/docs/thread14771.asp
Thank you all for help.
In fact the blinky example do not use I-Cache when running in internal RAM. By reading carefully the lpc3131 user manual one can read the following (Table 74. MMU translation table) :
PhyAdd 0x11000000 maps VirtAdd at 0x11000000 with cache disabled and write buffer disabled
But :
PhyAdd 0x11100000 maps VirtAdd at 0x11000000 with cache enabled and write buffer enabled
That means that the IRAM is mapped twice in the default MMU translation table, uncached at PhyAdd 0x11000000, and cached at 0x11100000. And in my system I only use internal RAM.
So to use caches, code must be mapped above 0x11100000.
Therefore I start to map my code in this way. However I need some help. I explain next what I have done : - I change the .ini script to start code at 0x11129000 - I change the ldscript to load code at 0x11129000 - I change the ISRAM_ESRAMX_BASE to 0x111xxxxx in the file lpc313x_chip.h - I change the END_OF_IRAM value to 0x11158000 in the startup assembly code - I force µVision to believe that LPC3131 RAM is located above 0x11100000 by modifying the .uv2 file ( Cpu (IRAM(0x11128000-0x1113FFFF) IRAM2(0x11140000-0x11157FFF) ....) - I enable only the I-cache in the startup assembly code
Doing this my program seems to start using debugger, but it crashes quickly. I have a "printf" at the beginning of my code, when I do step by step debugging the printf is executed but nothing goes out from UART. I try to do the same thing with a simpler example (blinky from C:\Keil\ARM\Boards\Embedded Artists\LPC3131\Blinky) with the same result.
I don't think that there is cache coherency issues since blinky code is only 800 Bytes long.
Maybe am I totally wrong with the above steps. Do you have any idea to achieve my goal ?
Best reagards
I do not think that there is a point in using caching for internal RAM as this is usually zero cycle RAM and caching makes no sense here. So caching makes sense for flash or SDRAM and I do not see a point in your using cache for internal RAM.
In fact I want to perform parallel transfer : - I want to copy data from USB to IRAM1 using USB AHB master - And in the same time to copy data from IRAM2 to MCI port using DMA controller
Each transfer taken appart offers good performances, but when I put them together performances are very low.
Therefore I wish to minimize data transfer over AHB matrix mainly for instruction fetch that generates activity on IRAM1. That's why I think I-cache may increase performances of my application.
Best regard
I don't think I cache would provide better performance in your case.
Why do you think so ? Don't you agree that CPU instruction fetch generates activity on the AHB matrix that should slow down my parallel DMA and USB transfers ?
I take the previous statement back, you should really benefit from using I-cache because of what you have written.