A bug in the startup file for LPC2400 ?

Hello,
I am new to the LPC2400 family so please bare in mind that I might be wrong!
When configuring my PLL, I noticed that the data sheet for the LPC2478 states, when describing the layout of the CCLKCFG register, that:

7:0 CCLKSEL Selects the divide value for creating the CPU clock (CCLK) from the
PLL output.
Only 0 and odd values (1, 3, 5, ..., 255) are supported and can be
used when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, ..., 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.

But the default startup file provided by Keil sets the value of CCLKCFG_Val to 4.